nexys4ddr數碼管動態掃描Verilog例程
阿新 • • 發佈：2018-05-13
IT CA set edi OS ssi dict ref 十六進制
題目：實現數碼管動態掃描功能，將十六個開關的值以十六進制的方式在4個數碼管上同時顯示出來。
`timescale 1ns / 1ps module top( clk, sw, seg, an ); //FPGA時鐘 input [15:0] sw; // 16位撥動開關，其中SW[0]可用於作為復位信號rst input clk; output [7:0] seg; // 8段數碼管驅動，低電平有效 output [7:0] an; // 8段數碼管片選信號，低電平有效 wire[31:0] data; //待顯示內容 wire clk1000Hz, clk100Hz, clk10Hz, clk1Hz;//1000/100/10/1Hz的時鐘 FrequencyDivider U_FRQNCYDVD(clk, clk1000Hz, clk100Hz, clk10Hz, clk1Hz);//分頻器 SevenSegDisp U_DISP(clk1000Hz, sw,seg, an);
module FrequencyDivider (clk, clk1000Hz, clk100Hz, clk10Hz, clk1Hz);//分頻器 input clk; //系統時鐘 output reg clk1000Hz; // 分頻後的時鐘1000Hz output reg clk100Hz; //分頻後的時鐘100Hz output reg clk10Hz; //分頻後的時鐘10Hz output reg clk1Hz; // 分頻後的時鐘1Hz parameter N1000 = 50_000; // 1000Hz的時鐘,N=fclk/fclk_N parameter N100 = 50_000_0; // 1000Hz的時鐘,N=fclk/fclk_N parameter N10 = 50_000_00; //1000Hz的時鐘,N=fclk/fclk_N parameter N1 = 50_000_000; // 1Hz的時鐘,N=fclk/fclk_N reg [31:0] counter1000, counter100, counter10, counter1; /* 計數器變量，通過計數實現分頻。 當計數器從0計數到(N/2-1)時， 輸出時鐘翻轉，計數器清零 */ always @(posedge clk) begin // 時鐘上升沿 if(counter1000==N1000) begin clk1000Hz <= ~clk1000Hz; counter1000 <= 32‘h0; end else counter1000 <= counter1000 + 1; end always @(posedge clk) begin // 時鐘上升沿 if(counter100==N100) begin clk100Hz <= ~clk100Hz; counter100 <= 32‘h0; end else counter100 <= counter100 + 1; end always @(posedge clk) begin // 時鐘上升沿 if(counter10==N10) begin clk10Hz <= ~clk10Hz; counter10 <= 32‘h0; end else counter10 <= counter10 + 1; end always @(posedge clk) begin // 時鐘上升沿 if(counter1==N1) begin clk1Hz <= ~clk1Hz; counter1 <= 32‘h0; end else counter1 <= counter1 + 1; end endmodule
`timescale 20ms / 1ms module SevenSegDisp(clk,sw,seg,an); input clk; input [15:0] sw; // 16位撥動開關 output [7:0] seg; // 7段數碼管驅動，低電平有效 output [7:0] an; // 7段數碼管片選信號，低電平有效 reg [1:0] q; wire [3:0] data; initial begin q=2‘b00; end // Counter8 U_CNT(clk,q); always @(posedge clk ) begin q<=q+1; if (q==2‘b11) q= 2‘b00; else q = q; end Mem U_MEM (q,sw,data); Decoder3_8 U_D38(q, an); //片選 SevenSegDecoder U_SSD1(data,seg); //8段碼 endmodule
`timescale 20ms / 1ms module Mem (num,sw,data); input [1:0] num; input [15:0] sw; output [3:0] data; reg [3:0] mem [3:0]; // initial // begin // assign sw=16‘h0000; // end assign data = mem[num]; always @(*) begin mem[0] = sw[3:0]; mem[1] = sw[7:4]; mem[2] = sw[11:8]; mem[3] = sw[15:12]; end endmodule
`timescale 20ms / 1ms module Decoder3_8(num, sel); input [1: 0] num; // 數碼管編號：0~7 output reg [7:0] sel; // 7段數碼管片選信號，低電平有效 always @(num) begin case(num) 3‘d0: sel = #10000000 8‘b11111110; 3‘d1: sel = #10000000 8‘b11111101; 3‘d2: sel = #10000000 8‘b11111011; 3‘d3: sel = #10000000 8‘b11110111; default: sel = 8‘b11111111; endcase end endmodule
module SevenSegDecoder( data, segments ); input [3:0] data; output [7:0] segments; assign segments = {dp, cg, cf, ce, cd, cc, cb, ca}; reg dp, cg, cf, ce, cd, cc, cb, ca; always @(data) begin case(data) 4‘h0: {ca, cb, cc, cd, ce, cf, cg, dp} = 8‘b0000_0011; 4‘h1: {ca, cb, cc, cd, ce, cf, cg, dp} = 8‘b1001_1111; 4‘h2: {ca, cb, cc, cd, ce, cf, cg, dp} = 8‘b0010_0101; 4‘h3: {ca, cb, cc, cd, ce, cf, cg, dp} = 8‘b0000_1101; 4‘h4: {ca, cb, cc, cd, ce, cf, cg, dp} = 8‘b1001_1001; 4‘h5: {ca, cb, cc, cd, ce, cf, cg, dp} = 8‘b0100_1001; 4‘h6: {ca, cb, cc, cd, ce, cf, cg, dp} = 8‘b0100_0001; 4‘h7: {ca, cb, cc, cd, ce, cf, cg, dp} = 8‘b0001_1111; 4‘h8: {ca, cb, cc, cd, ce, cf, cg, dp} = 8‘b0000_0001; 4‘h9: {ca, cb, cc, cd, ce, cf, cg, dp} = 8‘b0001_1001; 4‘ha: {ca, cb, cc, cd, ce, cf, cg, dp} = 8‘b0001_0001; 4‘hb: {ca, cb, cc, cd, ce, cf, cg, dp} = 8‘b1100_0001; 4‘hc: {ca, cb, cc, cd, ce, cf, cg, dp} = 8‘b1110_0101; 4‘hd: {ca, cb, cc, cd, ce, cf, cg, dp} = 8‘b1000_0101; 4‘he: {ca, cb, cc, cd, ce, cf, cg, dp} = 8‘b0110_0001; 4‘hf: {ca, cb, cc, cd, ce, cf, cg, dp} = 8‘b0111_0001; default: {ca, cb, cc, cd, ce, cf, cg, dp} = 8‘b1111_1111; endcase end endmodule
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK}];
set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }];
set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8]
set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9]
set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12]
set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
##7 segment display
set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { seg[0] }]; #ca
set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { seg[1] }]; #cb
set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { seg[2] }]; #cc
set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { seg[3] }]; #cd
set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { seg[4] }]; #ce
set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { seg[5] }]; #cf
set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { seg[6] }]; #cg
set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { seg[7] }]; #dp
set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #an[0]
set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #an[1]
set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #an[2]
set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #an[3]
set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #an[4]
set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #an[5]
set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #an[6]
set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #an[7]
nexys4ddr數碼管動態掃描Verilog例程