1. 程式人生 > >關於Verilog HDL的一些技巧、易錯、易忘點 daily record

關於Verilog HDL的一些技巧、易錯、易忘點 daily record

  1. 一個小細節
[email protected](posedge I_clk)
   begin
      if(I_rst_p)
         cnt <= 2'd0;
      else if(cnt == 2'd2)
         cnt <= 2'd0;
      else
         cnt <= cnt + 1;          
   end

[email protected](posedge I_clk)
   begin
      if(I_rst_p)
         O_a <= 1
'b0; else if((cnt == 2'd1) & valid) O_a <= 1'b1; else O_a <= 1'b0; end [email protected](posedge I_clk) begin if(I_rst_p) O_b <= 1'b0; else O_b <= ((cnt == 2'd1) & valid); end assign valid = (cnt == 2'd1);

模擬如下:


這裡寫圖片描述