chapter 5: tlp elements (details of tlp)

chapter 6: flow control

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digest (end to end CRC, ECRC)

HDR + DATA + DIGEST =  TLP

seq num +  TLP + CRC : DLL

STP + DLL + END : PL

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1. 

flow-control buffers are maintained separately ( VC各自有各自的FLOW CONTROL BUFFER)

pcie supports up to 8 Virtual Channels

2.

credit-based mechanism

initialization stage & run-time stage (using Flow Control DLLPs to updates) （初始階段與執行時階段）

3.

VC flow control buffer category:

posted transactions: memory writes and messages

non-posted transactions: memory reads, configuration reads and writes, and io reads and writes

completions: read and write completions

each category is separated into header and data portions

PH, PD, NPH, NPD, CPLH, CPLD （VC BUFFER的分類）

4.

link up signal from physical layer to data link layer (physical layer link training completed) （LINK UP訊號）

5.

DLCMSM: data link control and management state machine （DLCMSM狀態機，及各狀態的跳轉條件與各狀態時的行為動作）

DL_Inactive --> DL_Init (FC_Init1, FC_Init2) --> DL_Active

reset  -->  DL_Inactive (action: DL_Down signal to both DLL and TL)  --> DL_Init sub-state (condition: phy link up)

FC_Init1 (action: sequence of 3 InitFC1)

FC_Init2 (action: sequence of InitFC2, confirm FC initialization has succeeded at the sender, DL_up to TL)