TMS320F28335時鐘

    TMS320F28335上有一個基於PLL電路的片上時鐘模組，如圖1所示，為CPU及外設提供時鐘有兩種方式：

      一種是用外部的時鐘源，將其連線到X1引腳上或者XCLKIN引腳上，X2接地；

      另一種是使用振盪器產生時鐘，用30MHz的晶體和兩個20PF的電容組成的電路分別連線到X1和X2引腳上，XCLKIN引腳接地。

    我們常用第二種來產生時鐘。此時鐘將通過一個內部PLL鎖相環電路，進行倍頻。由於F28335的最大工作頻率是150M，所以倍頻值最大是5。其中倍頻值由PLLCR的低四位和PLLSTS的第7、8位來決定。其詳細的倍頻值可以參照TMS320F28335的Datasheet。

三種時鐘輸入的接法：

下面是InitSysCtrl函式中呼叫的InitPll函式進行時鐘設定：

//---------------------------------------------------------------------------
// This function initializes the PLLCR register.

void InitPll(Uint16 val, Uint16 divsel)
{

   // Make sure the PLL is not running in limp mode
   if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 0)
   {
      // Missing external clock has been detected
      // Replace this line with a call to an appropriate
      // SystemShutdown(); function.
      asm("        ESTOP0");
   }

   // DIVSEL MUST be 0 before PLLCR can be changed from
   // 0x0000. It is set to 0 by an external reset XRSn
   // This puts us in 1/4
   if (SysCtrlRegs.PLLSTS.bit.DIVSEL != 0)
   {
       EALLOW;
       SysCtrlRegs.PLLSTS.bit.DIVSEL = 0;
       EDIS;
   }

   // Change the PLLCR
   if (SysCtrlRegs.PLLCR.bit.DIV != val)
   {

      EALLOW;
      // Before setting PLLCR turn off missing clock detect logic
      SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1;
      SysCtrlRegs.PLLCR.bit.DIV = val;
      EDIS;

      // Optional: Wait for PLL to lock.
      // During this time the CPU will switch to OSCCLK/2 until
      // the PLL is stable.  Once the PLL is stable the CPU will
      // switch to the new PLL value.
      //
      // This time-to-lock is monitored by a PLL lock counter.
      //
      // Code is not required to sit and wait for the PLL to lock.
      // However, if the code does anything that is timing critical,
      // and requires the correct clock be locked, then it is best to
      // wait until this switching has completed.

      // Wait for the PLL lock bit to be set.

      // The watchdog should be disabled before this loop, or fed within
      // the loop via ServiceDog().

	  // Uncomment to disable the watchdog
      DisableDog();

      while(SysCtrlRegs.PLLSTS.bit.PLLLOCKS != 1)
      {
	      // Uncomment to service the watchdog
          // ServiceDog();
      }

      EALLOW;
      SysCtrlRegs.PLLSTS.bit.MCLKOFF = 0;
      EDIS;
    }

    // If switching to 1/2
	if((divsel == 1)||(divsel == 2))
	{
		EALLOW;
	    SysCtrlRegs.PLLSTS.bit.DIVSEL = divsel;
	    EDIS;
	}

	// If switching to 1/1
	// * First go to 1/2 and let the power settle
	//   The time required will depend on the system, this is only an example
	// * Then switch to 1/1
	if(divsel == 3)
	{
		EALLOW;
	    SysCtrlRegs.PLLSTS.bit.DIVSEL = 2;
	    DELAY_US(50L);
	    SysCtrlRegs.PLLSTS.bit.DIVSEL = 3;
	    EDIS;
    }
}
 

如果我們希望DSP工作在某一個頻率下，我們就可以對Uint16 val, Uint16 divsel兩個引數進行設定。

說白了就相當於乘10，除2 (30*10/2 = 150MHZ)

更詳細內容參考：

http://wenku.baidu.com/link?url=vL0bh97ETShHDNcARicm11dkcvSac4VbUE-mm9uvkZSxq4wDpYi3x9Xxevtq7moLFlBX3KSYSQ6icRGo21ePg7MWfu8hI4cnfrn_aAFRUUi