ECDSA—模加減模組

    // op = 1, a-b mod p
    // op = 0, a+b mod p
 
module mod_add(
    input             clk,
    input             reset,
    input             en,
    input     [255:0] a,
    input     [255:0] b,
    input             op,
    output     reg [255:0] sum,
    output     reg mod_add_done
);
    parameter params_p=256'd15424654874903;
    //parameter params_p = 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFC2F;
 
    reg [256:0] temp1;//temp2;                    //the [256] is the sign bit
 
    reg [1:0] cs,ns;
    parameter idle = 0;
    parameter s1 = 1;
    parameter s2 = 2;
    parameter s3 = 3;
 
    always@(posedge clk) begin
        if(reset)
            cs <= idle;
        else
            cs <= ns;
    end
 
    always@(*) begin
        case(cs)
        idle:
            ns <= s1;
        s1:
            ns <= s2;
        s2:
            if(temp1[256])
                ns <= s2;
            else if(temp1 >= params_p)
                ns <= s2;
            else
                ns <= s3;
        s3:
            ns <= en ? idle : s3;
        endcase
    end
 
    always@(*) begin
        case(cs)
        idle: begin
            sum <= 0;
            mod_add_done <= 0;
        end
        s1:
            if(op) begin
                temp1 <= a - b;
                //temp2 = temp1 + params_p;
            end
            else begin
                temp1 <= a + b;
                //temp2 = temp1 - params_p;
            end
        s2:
            if(op) begin
                if(temp1[256])    begin                //if temp1[256] is 1, 'a<b', 'a-b mod p' = 'params_p+(b-a)'
                    temp1 <= temp1 + params_p;
                end
                else if(temp1 >= params_p)
                    temp1 <= temp1 - params_p;
            end
            else begin
                if(temp1 >= params_p)                //if temp1[256] is 1, 'a<b', 'a-b mod p' = 'params_p-(b-a)'
                    temp1 <= temp1 - params_p;
                //else
                    //temp2 = temp1;
            end
        s3: begin
            sum <= temp1[255:0];
            mod_add_done <= 1;
        end
        endcase
    end
 
endmodule

`timescale 1ns/1ns
 
module mod_add_tb();
 
    reg clk, reset,en;
    reg [255:0] a, b;
    wire [255:0] sum;
    reg op;
    wire    mod_add_done;
 
    mod_add add0(
        .clk(clk),
        .reset(reset),
        .en(en),
        .a(a),
        .b(b),
        .sum(sum),
        .op(op),
        .mod_add_done(mod_add_done)
    );
 
    always #5 clk = ~clk;
 
    initial begin
        clk = 0;
 
        reset = 1'b1;
        en = 0;
 
        #20
        reset = 1'b0;
        op = 1;//P=29
        a = 256'd15424654874903;
        b =256'd15424654874906;
　　　　 #10000 $stop; 

end endmodule