Verilog RTL 程式碼設計新手上路（學生實驗1--4）
學生實驗
做一個4選1的mux，並且進行波形模擬 和2選1的mux對比，觀察資源消耗的變化
實驗程式碼設計如下：
module mux(
IN0 ,
IN1 ,
IN2 ,
IN3 ,
SEL0 ,
SEL1 ,
OUT );
parameter WL = 16;
input [WL-1:0] IN0,IN1,IN2,IN3;
input SEL0,SEL1;
output [WL-1:0] OUT;
reg OUT;
always @ (IN1 or IN2 or IN3 or SEL0 or SEL1) begin
case({SEL1,SEL0})
2’b00:OUT = IN0;
2’b01:OUT = IN1;
2’b10:OUT = IN2;
2’b11:OUT = IN3;
endcase
end
endmodule
波形模擬結果如圖：
資源消耗變化如下圖所示：
4選1的mux
2選1的mux
學生實驗
編寫一個4X4路交叉開關的RTL，然後編譯，看RTL View 比較2x2與4x4之間消耗資源的區別。通過對比資源，你有什麼結論？
實驗程式碼設計如下：
module mux4(
IN0,
IN1,
IN2,
IN3,
SEL0 ,
SEL1 ,
SEL2 ,
SEL3 ,
OUT0 ,
OUT1 ,
OUT2 ,
OUT3 );
parameter WL = 16;
input[WL-1:0] IN0,IN1,IN2,IN3;
input SEL0,SEL1,SEL2,SEL3;
output [WL-1:0] OUT0,OUT1,OUT2,OUT3;
reg[WL-1:0] OUT0,OUT1,OUT2,OUT3;
always @ (IN0 or IN1 or IN2 or IN3 or SEL0 or SEL1) begin
if((SEL0) && (SEL1))
OUT0 = IN3;
else if((!SEL0) && (SEL1))
OUT0 = IN2;
else if((SEL0) && (!SEL1))
OUT0 = IN1;
else
OUT0 = IN0;
end
always @ (IN0 or IN1 or IN2 or IN3 or SEL0 or SEL1) begin
if((SEL1) && (SEL2))
OUT1 = IN3;
else if((!SEL1) && (SEL2))
OUT1 = IN2;
else if((SEL1) && (!SEL2))
OUT1 = IN1;
else
OUT1 = IN0;
end
always @ (IN0 or IN1 or IN2 or IN3 or SEL0 or SEL1) begin
if((SEL2) && (SEL3))
OUT2 = IN3;
else if((!SEL2) && (SEL3))
OUT2 = IN2;
else if((SEL2) && (!SEL3))
OUT2 = IN1;
else
OUT2 = IN0;
end
always @ (IN0 or IN1 or IN2 or IN3 or SEL0 or SEL1) begin
if((SEL0) && (SEL3))
OUT3 = IN3;
else if((!SEL0) && (SEL3))
OUT3 = IN1;
else if((SEL0) && (!SEL3))
OUT3 = IN2;
else
OUT3 = IN0;
end
endmodule
RTL Viewer：
資源消耗對比如下圖：
4×4交叉開關
2×2交叉開關
學生實驗
編寫一個8輸入的優先編碼器，然後編譯，看RTL View
實驗程式碼設計如下：
module enc8(
IN ,
OUT );
input[7:0] IN;
output [3:0] OUT;
reg [3:0] OUT;
always @ (IN) begin
if(IN[7])
OUT = 4’b0111;
else if(IN[6])
OUT = 4’b0110;
else if(IN[5])
OUT = 4’b0101;
else if(IN[4])
OUT = 4’b0100;
else if(IN[3])
OUT = 4’b0011;
else if(IN[2])
OUT = 4’b0010;
else if(IN[1])
OUT = 4’b0001;
else if(IN[0])
OUT = 4’b0000;
else
OUT = 4’b1111;
end
endmodule
RTL Viewer:
學生實驗
編寫一個4－16的譯碼器，編譯
和3－8譯碼器對比資源開銷
看RTL View
實驗程式碼設計如下：
module enc4_16(
IN,
OUT);
input [3:0] IN;
output [15:0] OUT;
reg [15:0] OUT;
always @ (IN) begin
case(IN)
4’b0000:OUT = 16’b0000000000000001;
4’b0001:OUT = 16’b0000000000000010;
4’b0010:OUT = 16’b0000000000000100;
4’b0011:OUT = 16’b0000000000001000;
4’b0100:OUT = 16’b0000000000010000;
4’b0101:OUT = 16’b0000000000100000;
4’b0110:OUT = 16’b0000000001000000;
4’b0111:OUT = 16’b0000000010000000;
4’b1000:OUT = 16’b0000000100000000;
4’b1001:OUT = 16’b0000001000000000;
4’b1010:OUT = 16’b0000010000000000;
4’b1011:OUT = 16’b0000100000000000;
4’b1100:OUT = 16’b0001000000000000;
4’b1101:OUT = 16’b0100000000000000;
4’b1110:OUT = 16’b1000000000000000;
endcase
end
endmodule
RTL Viewer:
資源消耗對比：
4-16譯碼器
3-8譯碼器
