濾掉小於1個週期glitch的原理圖如下： 
 
verilog程式碼實現如下：

module digital_filter_(clk_in,rst,host_rst,host_rst_filter);
input  clk_in;
input  rst;
input  host_rst;
output host_rst_filter;

reg host_rst_d1;
reg host_rst_d2;

[email protected](posedge clk_in or negedge rst)
  begin
    if(~rst)
    begin
        host_rst_d1 <= 1'b1;
        host_rst_d2 <= 1'b1;
       end
    else
      begin
        host_rst_d1 <= host_rst;
        host_rst_d2 <= host_rst_d1;

      end
  end

assign host_rst_filter = host_rst_d1 | host_rst_d2;

endmodule
 

濾掉大於1個週期且小於2個週期glitch的原理圖如下：

verilog程式碼實現如下：

module digital_filter_(clk_in,rst,host_rst,host_rst_filter);
input  clk_in;
input  rst;
input  host_rst;
output host_rst_filter;

reg host_rst_d1;
reg host_rst_d2;
reg host_rst_d3;

[email protected](posedge clk_in or negedge rst)
  begin
    if(~rst)
    begin
        host_rst_d1 <= 1'b1;
        host_rst_d2 <= 1'b1;
        host_rst_d3 <= 1'b1;
      end
    else
  begin
        host_rst_d1 <= host_rst;
        host_rst_d2 <= host_rst_d1;
        host_rst_d3 <= host_rst_d2;
       end
  end

assign host_rst_filter = host_rst_d1 | host_rst_d2 | host_rst_d3;

endmodule