Verilog奇偶分頻電路的總結
阿新 • • 發佈:2018-12-03
1、偶數分頻
偶數倍分頻相對簡單,可以通過計數器對預分頻的脈衝沿計數實現,如果要進行N倍(N為整數)偶數分頻,可由預分頻的時鐘觸發計數器計數,當計數器從0計數到N/2—1時,輸出時鐘進行翻轉,並給計數器一個復位訊號,使得下一個時鐘從零開始計數,以此迴圈下去。分頻的主體程式如下:
module freq_div_even(input clk_in, input reset, output reg clk_out ); reg[2:0] count; parameter N=8; [email protected](posedge clk_in) begin if(!reset) begin count<=0; clk_out<=0; end else if(count==(N/2-1)) begin clk_out<=~clk_out; count<=0; end else begin count<=count+1; end end endmodule
2、奇數分頻
對於對佔空比沒有特殊要求的奇數分頻,需要對上升沿和下降沿脈衝進行計數,利用下降沿產生的波形移相半個輸入脈衝的作用,最後用錯位“異或”法實現。一個13分頻的程式如下:
module count_num(
input clk,
input reset,
output cout//這裡是wire型變數
);
reg[4:0] m,n;
reg cout1,cout2;
assign cout = cout1 | cout2//**口訣:模組輸入端必須用wire,模組輸出端可以用wire,reg,assign必須用wire,always必須用reg**
[email protected] (posedge clk)
begin
if(!reset)
begin cout1<=0; m<=0; end
else
begin
if(m=NUM-1)
m<=0;
else
m<=m+1;
if(m<(NUM-1)/2)
cout1<=1;
else
cout1<=0;
end
end
[email protected](negedge clk)
begin
if(!reset)
begin cout2<=0; n<=0; end
else
begin
if(n=NUM-1)
n<=0;
else
n<=n+1;
if(n<(NUM-1)/2)
cout2<=1;
else
cout2<=0;
end
end
endmodule