開源uvm reg model (UVM 暫存器模型)生成工具
阿新 • • 發佈：2018-12-12
open-register-design-tool
Ordt is a tool for automation of IC register definition and documentation. It currently supports 2 input formats:
- SystemRDL - a stardard register description format released by Accellera.org
- JSpec - a register description format used within Juniper Networks
The tool can generate several outputs from SystemRDL or JSpec, including:
- SystemVerilog/Verilog RTL code description of registers
- UVM model of the registers
- C++ models of the registers
- XML and text file register descriptions
- SystemRDL and JSpec (conversion)
Easiest way to get started with ordt is to download a runnable jar from the release area.
Ordt documentation can be found here.
注：nvdla中使用SystemRDL格式描述暫存器模型，並使用jar xxx ordt.jar ......生成uvm reg model