bl cache_on跳轉的返回
bl cache_on @ bl跳轉會將返回地址(下一條指令的地址)儲存到lr
轉載地址：https://blog.csdn.net/coldsnow33/article/details/37727331-
cache_on: mov r3, #8 @ cache_on function //偏移為8，對應cache_on -
b call_cache_fn @ b跳轉不會將返回地址儲存到lr
-
call_cache_fn: adr r12, proc_types -
#ifdef CONFIG_CPU_CP15 -
mrc p15, 0, r9, c0, c0 @ get processor ID -
#else -
ldr r9, =CONFIG_PROCESSOR_ID -
#endif -
1: ldr r1, [r12, #0] @ get value -
ldr r2, [r12, #4] @ get mask -
eor r1, r1, r9 @ (real ^ match) -
tst r1, r2 @ & mask -
ARM( addeq pc, r12, r3 ) @ call cache function -
THUMB( addeq r12, r3 ) -
THUMB( moveq pc, r12 ) @ call cache function//match到ID後就跳轉到對應架構的cache_on了 -
add r12, r12, #PROC_ENTRY_SIZE @ 沒有match到ID，PROC_ENTRY_SIZE為4*5，每條指令4byte,proc_types表中每個架構對應5個條目 -
b 1b @ 再跳轉回tag1時， r12儲存了下一個架構的條目，繼續match
-
.align 2 -
.type proc_types,#object -
proc_types: -
.word 0x41000000 @ old ARM ID -
.word 0xff00f000 -
mov pc, lr -
THUMB( nop ) -
mov pc, lr -
THUMB( nop ) -
mov pc, lr -
THUMB( nop ) -
.word 0x41007000 @ ARM7/710 -
.word 0xfff8fe00 -
mov pc, lr -
THUMB( nop ) -
mov pc, lr -
THUMB( nop ) -
mov pc, lr -
THUMB( nop ) -
.word 0x41807200 @ ARM720T (writethrough) -
.word 0xffffff00 -
W(b) __armv4_mmu_cache_on -
W(b) __armv4_mmu_cache_off -
mov pc, lr -
THUMB( nop ) -
.word 0x41007400 @ ARM74x -
.word 0xff00ff00 -
W(b) __armv3_mpu_cache_on -
W(b) __armv3_mpu_cache_off -
W(b) __armv3_mpu_cache_flush -
.word 0x41009400 @ ARM94x -
.word 0xff00ff00 -
W(b) __armv4_mpu_cache_on -
W(b) __armv4_mpu_cache_off -
W(b) __armv4_mpu_cache_flush -
.word 0x41069260 @ ARM926EJ-S (v5TEJ) -
.word 0xff0ffff0 -
W(b) __arm926ejs_mmu_cache_on -
W(b) __armv4_mmu_cache_off -
W(b) __armv5tej_mmu_cache_flush -
.word 0x00007000 @ ARM7 IDs -
.word 0x0000f000 -
mov pc, lr -
THUMB( nop ) -
mov pc, lr -
THUMB( nop ) -
mov pc, lr -
THUMB( nop ) -
@ Everything from here on will be the new ID system. -
.word 0x4401a100 @ sa110 / sa1100 -
.word 0xffffffe0 -
W(b) __armv4_mmu_cache_on -
W(b) __armv4_mmu_cache_off -
W(b) __armv4_mmu_cache_flush -
.word 0x6901b110 @ sa1110 -
.word 0xfffffff0 -
W(b) __armv4_mmu_cache_on -
W(b) __armv4_mmu_cache_off -
W(b) __armv4_mmu_cache_flush -
.word 0x56056900 -
.word 0xffffff00 @ PXA9xx -
W(b) __armv4_mmu_cache_on -
W(b) __armv4_mmu_cache_off -
W(b) __armv4_mmu_cache_flush -
.word 0x56158000 @ PXA168 -
.word 0xfffff000 -
W(b) __armv4_mmu_cache_on -
W(b) __armv4_mmu_cache_off -
W(b) __armv5tej_mmu_cache_flush -
.word 0x56050000 @ Feroceon -
.word 0xff0f0000 -
W(b) __armv4_mmu_cache_on -
W(b) __armv4_mmu_cache_off -
W(b) __armv5tej_mmu_cache_flush -
#ifdef CONFIG_CPU_FEROCEON_OLD_ID -
/* this conflicts with the standard ARMv5TE entry */ -
.long 0x41009260 @ Old Feroceon -
.long 0xff00fff0 -
b __armv4_mmu_cache_on -
b __armv4_mmu_cache_off -
b __armv5tej_mmu_cache_flush -
#endif -
.word 0x66015261 @ FA526 -
.word 0xff01fff1 -
W(b) __fa526_cache_on -
W(b) __armv4_mmu_cache_off -
W(b) __fa526_cache_flush -
@ These match on the architecture ID -
.word 0x00020000 @ ARMv4T -
.word 0x000f0000 -
W(b) __armv4_mmu_cache_on -
W(b) __armv4_mmu_cache_off -
W(b) __armv4_mmu_cache_flush -
.word 0x00050000 @ ARMv5TE -
.word 0x000f0000 -
W(b) __armv4_mmu_cache_on -
W(b) __armv4_mmu_cache_off -
W(b) __armv4_mmu_cache_flush -
.word 0x00060000 @ ARMv5TEJ -
.word 0x000f0000 -
W(b) __armv4_mmu_cache_on -
W(b) __armv4_mmu_cache_off -
W(b) __armv5tej_mmu_cache_flush -
.word 0x0007b000 @ ARMv6 -
.word 0x000ff000 -
W(b) __armv6_mmu_cache_on -
W(b) __armv4_mmu_cache_off -
W(b) __armv6_mmu_cache_flush -
.word 0x000f0000 @ new CPU Id -
.word 0x000f0000 -
W(b) __armv7_mmu_cache_on -
W(b) __armv7_mmu_cache_off -
W(b) __armv7_mmu_cache_flush -
.word 0 @ unrecognised type -
.word 0 -
mov pc, lr -
THUMB( nop ) -
mov pc, lr -
THUMB( nop ) -
mov pc, lr -
THUMB( nop ) -
.size proc_types, . - proc_types
如果ID沒有match，就會查到表中的最後一個條目，mov pc, lr，跳回去。
-
armv7_mmu_cache_on: -
mov r12, lr @ lr儲存的是bl cache_on的下一條指令,下面還有tag的跳轉，會重寫lr，需要儲存lr到其他暫存器#ifdef CONFIG_MMU -
mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0 -
tst r11, #0xf @ VMSA -
movne r6, #CB_BITS | 0x02 @ !XN -
blne __setup_mmu @ bl跳轉會儲存返回地址到lr -
mov r0, #0 -
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer -
tst r11, #0xf @ VMSA -
mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs -
#endif -
mrc p15, 0, r0, c1, c0, 0 @ read control reg -
bic r0, r0, #1 << 28 @ clear SCTLR.TRE -
orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement -
orr r0, r0, #0x003c @ write buffer -
bic r0, r0, #2 @ A (no unaligned access fault) -
orr r0, r0, #1 << 22 @ U (v6 unaligned access model) -
@ (needed for ARM1176) -
#ifdef CONFIG_MMU -
ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables -
mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg -
orrne r0, r0, #1 @ MMU enabled -
movne r1, #0xfffffffd @ domain 0 = client -
bic r6, r6, #1 << 31 @ 32-bit translation system -
bic r6, r6, #3 << 0 @ use only ttbr0 -
mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer -
mcrne p15, 0, r1, c3, c0, 0 @ load domain access control -
mcrne p15, 0, r6, c2, c0, 2 @ load ttb control -
#endif -
mcr p15, 0, r0, c7, c5, 4 @ ISB -
mcr p15, 0, r0, c1, c0, 0 @ load control register -
mrc p15, 0, r0, c1, c0, 0 @ and read it back -
mov r0, #0 -
mcr p15, 0, r0, c7, c5, 4 @ ISB -
mov pc, r12 @ 返回到bl cache_on的下一條指令