一直對協處理器CP15很恐懼，因為在網上基本上找不到中文的詳細說明，現在找了一些ARM官方文件（ARM920T Technical Reference Manual）來看，準備對它做個了結。

    協處理器CP15包含了如下暫存器。

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在ARM920T Technical Reference Manual中有如下關鍵術語

2.3.1 Addresses in ARM920TThree distinct types of address exist in an ARM920T system:• Virtual Address (VA)• Modified Virtual Address (MVA)• Physical Address (PA).

Below is an example of the address manipulation when the ARM9TDMI core requests an instruction (see Figure 2-10 on page 2-25).1. The Instruction VA (IVA) is issued by the ARM9TDMI core.2. This is translated by the ProcID to the Instruction MVA (IMVA). It is the IMVA that the Instruction Cache (ICache) and MMU see.3. If the protection check carried out by the IMMU on the IMVA does not abort, and the IMVA tag is in the ICache, the instruction data is returned to the ARM9TDMI core.4. If the ICache misses (the IMVA tag is not in the ICache), then the IMMU performs a translation to produce the Instruction PA (IPA). This address is given to the AMBA bus interface to perform an external access.

_________________________________________________這些東西我就不具體翻譯了，免得誤人子弟。

2.3.2 Accessing CP15 registers訪問CP15 暫存器The terms and abbreviations（縮寫詞） shown in Table 2-4 are used throughout this section.Table 2-4 CP15 abbreviationsTerm Abbreviation DescriptionUnpredictable UNP

For reads, the data returned when reading from this location is unpredictable. It can have any value.For writes, writing to this location causes unpredictable behavior, or an unpredictable change in device configuration.Should be zero

SBZ

When writing to this location, all bits of this field should be 0.

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You can only access CP15 registers with MRC and MCR instructions in a privileged mode.（特權模式）

MCR/MRC{cond} P15,opcode_1,Rd,CRn,CRm,opcode_2

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Instructions CDP, LDC, and STC, together with unprivileged MRC and MCR instructions to CP15, cause the undefined instruction trap to be taken（導致未定義...）. The CRn field of MRC and MCR instructions specifies the coprocessor register to access. The CRm field and opcode_2  fields specify a particular action when addressing registers. The L bit distinguishes between an MRC (L=1) and an MCR (L=0).——指明瞭CRn 和CRm 的作用。

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Note Attempting to read from a nonreadable register, or to write to a nonwritable register causes unpredictable results.The opcode_1, opcode_2, and CRm fields should be zero, except when the values specified are used to select the desired operations, in all instructions that access CP15. Using other values results in unpredictable behavior.

——這裡用意何在？等到下面看看程式碼才知道。

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Register 0, ID code register（讀晶片32位ID）This is a read-only register that returns a 32-bit device ID code.You can access the ID code register by reading CP15 register 0 with the opcode_2 field set to any value other than 1 (the CRm field should be zero when reading). For example:

MRC p15,0,Rd,c0,c0,0 ; returns ID register

——晶片ID代表含義

Table 2-5 Register 0, ID codeRegister bits Function                            Value31:24 ——Implementer                         0x41——這個是什麼意思？23:20—— Specification revision           0x119:16 ——Architecture (ARMv4T)     0x215:4—— Part number                           0x9203:0 ——Layout revision Revision

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2.3.4 Register 0, cache type register

This is a read-only register that contains information about the size and architecture of the caches, allowing operating systems to establish how to perform such operations as cache cleaning and lockdown. All ARMv4T and later cached processors contain this register, allowing RTOS vendors to produce future-proof versions of their operating systems.

You can access the cache type register by reading CP15 register 0 with the opcode_2 field set to 1. For example:MRC p15,0,Rd,c0,c0,1 ; returns cache details

——看上去這個topic特別複雜，我寫了也沒有用，最重要我極有可能出錯，所以停止這篇部落格

有什麼問題，請到論壇發帖，或者參考

轉載請標明:作者[email protected].桂林電子科技大學一系科協，原文地址：http://blog.csdn.net/gooogleman——如有錯誤，希望能夠留言指出;如果你有更加好的方法，也請在部落格後面留言，我會感激你的批評和分享。