linux裝置模型之mmc，sd子系統
阿新 • • 發佈：2019-02-02
struct mmc_host {
171 struct device *parent;
172 struct device class_dev;
173 int index; //編號
174 const struct mmc_host_ops *ops; //特定控制器的操作函式，這個很重要
175 unsigned int f_min;
176 unsigned int f_max;
177 unsigned int f_init;
178 u32 ocr_avail; //支援電壓範圍
179 u32 ocr_avail_sdio; /* SDIO-specific OCR */
180 u32 ocr_avail_sd; /* SD-specific OCR */
181 u32 ocr_avail_mmc; /* MMC-specific OCR */
182 struct notifier_block pm_notify;
183
184 #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
185 #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
186 #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
187 #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
188 #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
189 #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
190 #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
191 #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
192 #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
193 #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
194 #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
195 #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
196 #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
197 #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
198 #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
199 #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
200 #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
201
202 unsigned long caps; /* Host capabilities */
203
204 #define MMC_CAP_4_BIT_DATA (1 << 0) /* Can the host do 4 bit transfers */
205 #define MMC_CAP_MMC_HIGHSPEED (1 << 1) /* Can do MMC high-speed timing */
206 #define MMC_CAP_SD_HIGHSPEED (1 << 2) /* Can do SD high-speed timing */
207 #define MMC_CAP_SDIO_IRQ (1 << 3) /* Can signal pending SDIO IRQs */
208 #define MMC_CAP_SPI (1 << 4) /* Talks only SPI protocols */
209 #define MMC_CAP_NEEDS_POLL (1 << 5) /* Needs polling for card-detection */
210 #define MMC_CAP_8_BIT_DATA (1 << 6) /* Can the host do 8 bit transfers */
211 #define MMC_CAP_DISABLE (1 << 7) /* Can the host be disabled */
212 #define MMC_CAP_NONREMOVABLE (1 << 8) /* Nonremovable e.g. eMMC */
213 #define MMC_CAP_WAIT_WHILE_BUSY (1 << 9) /* Waits while card is busy */
214 #define MMC_CAP_ERASE (1 << 10) /* Allow erase/trim commands */
215 #define MMC_CAP_1_8V_DDR (1 << 11) /* can support */
216 /* DDR mode at 1.8V */
217 #define MMC_CAP_1_2V_DDR (1 << 12) /* can support */
218 /* DDR mode at 1.2V */
219 #define MMC_CAP_POWER_OFF_CARD (1 << 13) /* Can power off after boot */
220 #define MMC_CAP_BUS_WIDTH_TEST (1 << 14) /* CMD14/CMD19 bus width ok */
221 #define MMC_CAP_UHS_SDR12 (1 << 15) /* Host supports UHS SDR12 mode */
222 #define MMC_CAP_UHS_SDR25 (1 << 16) /* Host supports UHS SDR25 mode */
223 #define MMC_CAP_UHS_SDR50 (1 << 17) /* Host supports UHS SDR50 mode */
224 #define MMC_CAP_UHS_SDR104 (1 << 18) /* Host supports UHS SDR104 mode */
225 #define MMC_CAP_UHS_DDR50 (1 << 19) /* Host supports UHS DDR50 mode */
226 #define MMC_CAP_SET_XPC_330 (1 << 20) /* Host supports >150mA current at 3.3V */
227 #define MMC_CAP_SET_XPC_300 (1 << 21) /* Host supports >150mA current at 3.0V */
228 #define MMC_CAP_SET_XPC_180 (1 << 22) /* Host supports >150mA current at 1.8V */
229 #define MMC_CAP_DRIVER_TYPE_A (1 << 23) /* Host supports Driver Type A */
230 #define MMC_CAP_DRIVER_TYPE_C (1 << 24) /* Host supports Driver Type C */
231 #define MMC_CAP_DRIVER_TYPE_D (1 << 25) /* Host supports Driver Type D */
232 #define MMC_CAP_MAX_CURRENT_200 (1 << 26) /* Host max current limit is 200mA */
233 #define MMC_CAP_MAX_CURRENT_400 (1 << 27) /* Host max current limit is 400mA */
234 #define MMC_CAP_MAX_CURRENT_600 (1 << 28) /* Host max current limit is 600mA */
235 #define MMC_CAP_MAX_CURRENT_800 (1 << 29) /* Host max current limit is 800mA */
236 #define MMC_CAP_CMD23 (1 << 30) /* CMD23 supported. */
237 #define MMC_CAP_HW_RESET (1 << 31) /* Hardware reset */
238
239 unsigned int caps2; /* More host capabilities */
240
241 #define MMC_CAP2_BOOTPART_NOACC (1 << 0) /* Boot partition no access */
242 #define MMC_CAP2_CACHE_CTRL (1 << 1) /* Allow cache control */
243 #define MMC_CAP2_POWEROFF_NOTIFY (1 << 2) /* Notify poweroff supported */
244 #define MMC_CAP2_NO_MULTI_READ (1 << 3) /* Multiblock reads don't work */
245
246 mmc_pm_flag_t pm_caps; /* supported pm features */
247 unsigned int power_notify_type;
248 #define MMC_HOST_PW_NOTIFY_NONE 0
249 #define MMC_HOST_PW_NOTIFY_SHORT 1
250 #define MMC_HOST_PW_NOTIFY_LONG 2
251
252 #ifdef CONFIG_MMC_CLKGATE
253 int clk_requests; /* internal reference counter */
254 unsigned int clk_delay; /* number of MCI clk hold cycles */
255 bool clk_gated; /* clock gated */
256 struct work_struct clk_gate_work; /* delayed clock gate */
257 unsigned int clk_old; /* old clock value cache */
258 spinlock_t clk_lock; /* lock for clk fields */
259 struct mutex clk_gate_mutex; /* mutex for clock gating */
260 #endif
261
262 /* host specific block data */
263 unsigned int max_seg_size; /* see blk_queue_max_segment_size */
264 unsigned short max_segs; /* see blk_queue_max_segments */
265 unsigned short unused;
266 unsigned int max_req_size; /* maximum number of bytes in one req */
267 unsigned int max_blk_size; /* maximum size of one mmc block */
268 unsigned int max_blk_count; /* maximum number of blocks in one req */
269 unsigned int max_discard_to; /* max. discard timeout in ms */
270
271 /* private data */
272 spinlock_t lock; /* lock for claim and bus ops */
273
274 struct mmc_ios ios; /* current io bus settings */
275 u32 ocr; /* the current OCR setting */
276
277 /* group bitfields together to minimize padding */
278 unsigned int use_spi_crc:1;
279 unsigned int claimed:1; /* host exclusively claimed */
280 unsigned int bus_dead:1; /* bus has been released */
281 #ifdef CONFIG_MMC_DEBUG
282 unsigned int removed:1; /* host is being removed */
283 #endif
284
285 /* Only used with MMC_CAP_DISABLE */
286 int enabled; /* host is enabled */
287 int rescan_disable; /* disable card detection */
288 int nesting_cnt; /* "enable" nesting count */
289 int en_dis_recurs; /* detect recursion */
290 unsigned int disable_delay; /* disable delay in msecs */
291 struct delayed_work disable; /* disabling work */
292
293 struct mmc_card *card; /* device attached to this host */
294
295 wait_queue_head_t wq;
296 struct task_struct *claimer; /* task that has host claimed */
297 int claim_cnt; /* "claim" nesting count */
298
299 struct delayed_work detect;
300
301 const struct mmc_bus_ops *bus_ops; /* current bus driver */
302 unsigned int bus_refs; /* reference counter */
303
304 unsigned int sdio_irqs;
305 struct task_struct *sdio_irq_thread;
306 atomic_t sdio_irq_thread_abort;
307
308 mmc_pm_flag_t pm_flags; /* requested pm features */
309
310 #ifdef CONFIG_LEDS_TRIGGERS
311 struct led_trigger *led; /* activity led */
312 #endif
313
314 #ifdef CONFIG_REGULATOR
315 bool regulator_enabled; /* regulator state */
316 #endif
317
318 struct dentry *debugfs_root;
319
320 struct mmc_async_req *areq; /* active async req */
321
322 #ifdef CONFIG_FAIL_MMC_REQUEST
323 struct fault_attr fail_mmc_request;
324 #endif
325
326 unsigned long private[0] ____cacheline_aligned;
327 };
171 struct device *parent;
172 struct device class_dev;
173 int index; //編號
174 const struct mmc_host_ops *ops; //特定控制器的操作函式，這個很重要
175 unsigned int f_min;
176 unsigned int f_max;
177 unsigned int f_init;
178 u32 ocr_avail; //支援電壓範圍
179 u32 ocr_avail_sdio; /* SDIO-specific OCR */
180 u32 ocr_avail_sd; /* SD-specific OCR */
181 u32 ocr_avail_mmc; /* MMC-specific OCR */
182 struct notifier_block pm_notify;
183
184 #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
185 #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
186 #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
187 #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
188 #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
189 #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
190 #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
191 #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
192 #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
193 #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
194 #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
195 #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
196 #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
197 #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
198 #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
199 #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
200 #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
201
202 unsigned long caps; /* Host capabilities */
203
204 #define MMC_CAP_4_BIT_DATA (1 << 0) /* Can the host do 4 bit transfers */
205 #define MMC_CAP_MMC_HIGHSPEED (1 << 1) /* Can do MMC high-speed timing */
206 #define MMC_CAP_SD_HIGHSPEED (1 << 2) /* Can do SD high-speed timing */
207 #define MMC_CAP_SDIO_IRQ (1 << 3) /* Can signal pending SDIO IRQs */
208 #define MMC_CAP_SPI (1 << 4) /* Talks only SPI protocols */
209 #define MMC_CAP_NEEDS_POLL (1 << 5) /* Needs polling for card-detection */
210 #define MMC_CAP_8_BIT_DATA (1 << 6) /* Can the host do 8 bit transfers */
211 #define MMC_CAP_DISABLE (1 << 7) /* Can the host be disabled */
212 #define MMC_CAP_NONREMOVABLE (1 << 8) /* Nonremovable e.g. eMMC */
213 #define MMC_CAP_WAIT_WHILE_BUSY (1 << 9) /* Waits while card is busy */
214 #define MMC_CAP_ERASE (1 << 10) /* Allow erase/trim commands */
215 #define MMC_CAP_1_8V_DDR (1 << 11) /* can support */
216 /* DDR mode at 1.8V */
217 #define MMC_CAP_1_2V_DDR (1 << 12) /* can support */
218 /* DDR mode at 1.2V */
219 #define MMC_CAP_POWER_OFF_CARD (1 << 13) /* Can power off after boot */
220 #define MMC_CAP_BUS_WIDTH_TEST (1 << 14) /* CMD14/CMD19 bus width ok */
221 #define MMC_CAP_UHS_SDR12 (1 << 15) /* Host supports UHS SDR12 mode */
222 #define MMC_CAP_UHS_SDR25 (1 << 16) /* Host supports UHS SDR25 mode */
223 #define MMC_CAP_UHS_SDR50 (1 << 17) /* Host supports UHS SDR50 mode */
224 #define MMC_CAP_UHS_SDR104 (1 << 18) /* Host supports UHS SDR104 mode */
225 #define MMC_CAP_UHS_DDR50 (1 << 19) /* Host supports UHS DDR50 mode */
226 #define MMC_CAP_SET_XPC_330 (1 << 20) /* Host supports >150mA current at 3.3V */
227 #define MMC_CAP_SET_XPC_300 (1 << 21) /* Host supports >150mA current at 3.0V */
228 #define MMC_CAP_SET_XPC_180 (1 << 22) /* Host supports >150mA current at 1.8V */
229 #define MMC_CAP_DRIVER_TYPE_A (1 << 23) /* Host supports Driver Type A */
230 #define MMC_CAP_DRIVER_TYPE_C (1 << 24) /* Host supports Driver Type C */
231 #define MMC_CAP_DRIVER_TYPE_D (1 << 25) /* Host supports Driver Type D */
232 #define MMC_CAP_MAX_CURRENT_200 (1 << 26) /* Host max current limit is 200mA */
233 #define MMC_CAP_MAX_CURRENT_400 (1 << 27) /* Host max current limit is 400mA */
234 #define MMC_CAP_MAX_CURRENT_600 (1 << 28) /* Host max current limit is 600mA */
235 #define MMC_CAP_MAX_CURRENT_800 (1 << 29) /* Host max current limit is 800mA */
236 #define MMC_CAP_CMD23 (1 << 30) /* CMD23 supported. */
237 #define MMC_CAP_HW_RESET (1 << 31) /* Hardware reset */
238
239 unsigned int caps2; /* More host capabilities */
240
241 #define MMC_CAP2_BOOTPART_NOACC (1 << 0) /* Boot partition no access */
242 #define MMC_CAP2_CACHE_CTRL (1 << 1) /* Allow cache control */
243 #define MMC_CAP2_POWEROFF_NOTIFY (1 << 2) /* Notify poweroff supported */
244 #define MMC_CAP2_NO_MULTI_READ (1 << 3) /* Multiblock reads don't work */
245
246 mmc_pm_flag_t pm_caps; /* supported pm features */
247 unsigned int power_notify_type;
248 #define MMC_HOST_PW_NOTIFY_NONE 0
249 #define MMC_HOST_PW_NOTIFY_SHORT 1
250 #define MMC_HOST_PW_NOTIFY_LONG 2
251
252 #ifdef CONFIG_MMC_CLKGATE
253 int clk_requests; /* internal reference counter */
254 unsigned int clk_delay; /* number of MCI clk hold cycles */
255 bool clk_gated; /* clock gated */
256 struct work_struct clk_gate_work; /* delayed clock gate */
257 unsigned int clk_old; /* old clock value cache */
258 spinlock_t clk_lock; /* lock for clk fields */
259 struct mutex clk_gate_mutex; /* mutex for clock gating */
260 #endif
261
262 /* host specific block data */
263 unsigned int max_seg_size; /* see blk_queue_max_segment_size */
264 unsigned short max_segs; /* see blk_queue_max_segments */
265 unsigned short unused;
266 unsigned int max_req_size; /* maximum number of bytes in one req */
267 unsigned int max_blk_size; /* maximum size of one mmc block */
268 unsigned int max_blk_count; /* maximum number of blocks in one req */
269 unsigned int max_discard_to; /* max. discard timeout in ms */
270
271 /* private data */
272 spinlock_t lock; /* lock for claim and bus ops */
273
274 struct mmc_ios ios; /* current io bus settings */
275 u32 ocr; /* the current OCR setting */
276
277 /* group bitfields together to minimize padding */
278 unsigned int use_spi_crc:1;
279 unsigned int claimed:1; /* host exclusively claimed */
280 unsigned int bus_dead:1; /* bus has been released */
281 #ifdef CONFIG_MMC_DEBUG
282 unsigned int removed:1; /* host is being removed */
283 #endif
284
285 /* Only used with MMC_CAP_DISABLE */
286 int enabled; /* host is enabled */
287 int rescan_disable; /* disable card detection */
288 int nesting_cnt; /* "enable" nesting count */
289 int en_dis_recurs; /* detect recursion */
290 unsigned int disable_delay; /* disable delay in msecs */
291 struct delayed_work disable; /* disabling work */
292
293 struct mmc_card *card; /* device attached to this host */
294
295 wait_queue_head_t wq;
296 struct task_struct *claimer; /* task that has host claimed */
297 int claim_cnt; /* "claim" nesting count */
298
299 struct delayed_work detect;
300
301 const struct mmc_bus_ops *bus_ops; /* current bus driver */
302 unsigned int bus_refs; /* reference counter */
303
304 unsigned int sdio_irqs;
305 struct task_struct *sdio_irq_thread;
306 atomic_t sdio_irq_thread_abort;
307
308 mmc_pm_flag_t pm_flags; /* requested pm features */
309
310 #ifdef CONFIG_LEDS_TRIGGERS
311 struct led_trigger *led; /* activity led */
312 #endif
313
314 #ifdef CONFIG_REGULATOR
315 bool regulator_enabled; /* regulator state */
316 #endif
317
318 struct dentry *debugfs_root;
319
320 struct mmc_async_req *areq; /* active async req */
321
322 #ifdef CONFIG_FAIL_MMC_REQUEST
323 struct fault_attr fail_mmc_request;
324 #endif
325
326 unsigned long private[0] ____cacheline_aligned;
327 };