深入詳解保護模式下的記憶體分頁機制
阿新 • • 發佈：2019-02-05
以下是Intel文件中關於分頁機制的詳細描述：
IA-32 Memory Models
When employing the processor’s memory management facilities, programs do not — 使用處理器記憶體管理設施時程式不會
directly address physical memory. Instead, they access memory using one of three 直接定址實體記憶體
memory models: flat, segmented, or real address mode:
• Flat memory model
address space (Figure 3-3). This space is called a linear address space. Code, 空間，這被稱為線性地址空間。要注意此時的
data, and stacks are all contained in this address space. Linear address space is 線性地址是保護模式下的。
byte addressable, with addresses running contiguously from 0 to 232
64-bit mode). An address for any byte in linear address space is called a linear
address.
• Segmented memory model — Memory appears to a program as a group of — 對於程式來說就像一系列獨立的地址空間的記憶體
independent address spaces called segments. Code, data, and stacks are 被稱為段。注意關鍵的地方來了，先解釋一下：
typically contained in separate segments. To address a byte in a segment, a
program issues a logical address. This consists of a segment selector and an 邏輯地址。它由段選擇子和一個偏移量所組成。
offset (logical addresses are often referred to as far pointers). The segment (注意只有保護模式下的段暫存器中才會
selector identifies the segment to be accessed and the offset identifies a byte in 有段選擇子)。
the address space of the segment. Programs running on an IA-32 processor can
address up to 16,383 segments of different sizes and types, and each segment
can be as large as 232 bytes.
• Real-address mode memory model — This is the memory model for the Intel — 這個記憶體模型是為8086處理器所使用的，使用
8086 processor. It is supported to provide compatibility with existing programs 它是為了與執行在8086上的已有程式提供相容性。
written to run on the Intel 8086 processor. The real-address mode uses a specific
implementation of segmented memory in which the linear address space for the
program and the operating system/executive consists of an array of segments of
up to 64 KBytes in size each. The maximum size of the linear address space in 注意這裡：線性地址空間的最大尺寸為1MB，
real-address mode is 220 bytes. 說明該記憶體模型在真實模式下使用。
Paging and Virtual Memory
With the flat or the segmented memory model, linear address space is — 最重要的地方來了：在平坦或是段式記憶體模型
mapped into the processor’s physical address space either directly or 下，線性地址或是直接或是通過分頁方式被對映到
through paging. When using direct mapping (paging disabled), each linear 處理器的實體地址空間。當分頁禁用而直接對映
address has a one-to-noe correspondence with a physical address. Linear 時線性地址與實體地址一一對應。線性地址不
addresses are sent out on the processor's address lines without translation. 通過轉換而直接送至處理器的地址空間中。
When using the IA-32 architecture’s paging mechanism (paging enabled), linear — 當使用32位體系結構的分頁機制時，線性
address space is divided into pages which are mapped to virtual memory. 地址空間被分割成對映至虛擬記憶體的頁。隨後
The pages of virtual memory are then mapped as needed into physical memory. 虛擬記憶體中的這些頁被對映至實體記憶體。
When an operating system or executive uses paging, the paging mechanism (這裡直接略過虛擬記憶體，和我們的分析無關)
is transparent to an application program. All that the application sees is
linear address space.
由上述最後一段話我們發現分頁機制的實施只囊括了平坦記憶體模型（Flat Memory Model）或段式記憶體模型（Segmented Memory Model），而這兩種模型根據分析知道都是在保護模式下才存在，處理器的分頁機制壓根就沒有提及實地址模式記憶體模型，因此在真實模式下無法使用分頁機制。
IA-32 Memory Models
When employing the processor’s memory management facilities, programs do not — 使用處理器記憶體管理設施時程式不會
directly address physical memory. Instead, they access memory using one of three 直接定址實體記憶體
memory models: flat, segmented, or real address mode:
• Flat memory model
address space (Figure 3-3). This space is called a linear address space. Code, 空間，這被稱為線性地址空間。要注意此時的
data, and stacks are all contained in this address space. Linear address space is 線性地址是保護模式下的。
byte addressable, with addresses running contiguously from 0 to 232
64-bit mode). An address for any byte in linear address space is called a linear
address.
• Segmented memory model — Memory appears to a program as a group of — 對於程式來說就像一系列獨立的地址空間的記憶體
independent address spaces called segments. Code, data, and stacks are 被稱為段。注意關鍵的地方來了，先解釋一下：
typically contained in separate segments. To address a byte in a segment, a
program issues a logical address. This consists of a segment selector and an 邏輯地址。它由段選擇子和一個偏移量所組成。
offset (logical addresses are often referred to as far pointers). The segment (注意只有保護模式下的段暫存器中才會
selector identifies the segment to be accessed and the offset identifies a byte in 有段選擇子)。
the address space of the segment. Programs running on an IA-32 processor can
address up to 16,383 segments of different sizes and types, and each segment
can be as large as 232 bytes.
• Real-address mode memory model — This is the memory model for the Intel — 這個記憶體模型是為8086處理器所使用的，使用
8086 processor. It is supported to provide compatibility with existing programs 它是為了與執行在8086上的已有程式提供相容性。
written to run on the Intel 8086 processor. The real-address mode uses a specific
implementation of segmented memory in which the linear address space for the
program and the operating system/executive consists of an array of segments of
up to 64 KBytes in size each. The maximum size of the linear address space in 注意這裡：線性地址空間的最大尺寸為1MB，
real-address mode is 220 bytes. 說明該記憶體模型在真實模式下使用。
Paging and Virtual Memory
With the flat or the segmented memory model, linear address space is — 最重要的地方來了：在平坦或是段式記憶體模型
mapped into the processor’s physical address space either directly or 下，線性地址或是直接或是通過分頁方式被對映到
through paging. When using direct mapping (paging disabled), each linear 處理器的實體地址空間。當分頁禁用而直接對映
address has a one-to-noe correspondence with a physical address. Linear 時線性地址與實體地址一一對應。線性地址不
addresses are sent out on the processor's address lines without translation. 通過轉換而直接送至處理器的地址空間中。
When using the IA-32 architecture’s paging mechanism (paging enabled), linear — 當使用32位體系結構的分頁機制時，線性
address space is divided into pages which are mapped to virtual memory. 地址空間被分割成對映至虛擬記憶體的頁。隨後
The pages of virtual memory are then mapped as needed into physical memory. 虛擬記憶體中的這些頁被對映至實體記憶體。
When an operating system or executive uses paging, the paging mechanism (這裡直接略過虛擬記憶體，和我們的分析無關)
is transparent to an application program. All that the application sees is
linear address space.
由上述最後一段話我們發現分頁機制的實施只囊括了平坦記憶體模型（Flat Memory Model）或段式記憶體模型（Segmented Memory Model），而這兩種模型根據分析知道都是在保護模式下才存在，處理器的分頁機制壓根就沒有提及實地址模式記憶體模型，因此在真實模式下無法使用分頁機制。