complie error類

在錯誤的位置賦值或assign

module mod(
    );
    wire w;
    reg r;
    assign w = 1;             // 正確,在initial或always之assign
    r = 0;                    // 錯誤，在initial或always之外賦值
    assign r = 0;             // 錯誤，在initial或always之外賦值
    initial begin
        assign w = 0;         // 錯誤，在initial或always之內assign
        r = 1
 
;                // 正確，在initial或always之內賦值
        assign r = 0;         // 正確，在initial或always之內賦值
    end
endmodule

[USF-XSim 62] ‘compile’ step failed with error(s) while executing ‘D:/vivado/LED_8light/LED_8light.sim/sim_1/behav/compile.bat’ script. Please check that the file has the correct ‘read/write/execute’ permissions and the Tcl console output for any other possible errors or warnings.

使用了未定義的變數

[USF-XSim-62] ‘compile’ step failed with error(s) while executing ‘D:/vivado/LED_8light/LED_8light.sim/sim_1/behav/compile.bat’ script. Please check that the file has the correct ‘read/write/execute’ permissions and the Tcl console output for any other possible errors or warnings.

在always塊中宣告變數

always @(count or reset) begin
    reg [7:0] Y;
end

[USF-XSim 62] ‘compile’ step failed with error(s) while executing ‘D:/vivado/LED_8light/LED_8light.sim/sim_1/behav/compile.bat’ script. Please check that the file has the correct ‘read/write/execute’ permissions and the Tcl console output for any other possible errors or warnings.

重複宣告變數

reg [7:0] Y;
wire Y;

[USF-XSim 62] ‘compile’ step failed with error(s) while executing ‘D:/vivado/LED_8light/LED_8light.sim/sim_1/behav/compile.bat’ script. Please check that the file has the correct ‘read/write/execute’ permissions and the Tcl console output for any other possible errors or warnings.

語法錯誤

• 引數間沒有加逗號
• 引數最後加了分號
• 引數前面沒加input或output
• 引數個數不匹配
  

[USF-XSim 62] ‘compile’ step failed with error(s) while executing ‘D:/vivado/LED_8light/LED_8light.sim/sim_1/behav/compile.bat’ script. Please check that the file has the correct ‘read/write/execute’ permissions and the Tcl console output for any other possible errors or warnings.

在錯誤的地方使用inut/output

module multiplier_sim();
    input reg[31:0] multiplicand;
    input reg[31:0] multiplier;
    input wire[31:0] product;
    // 錯誤：input/output不能定義在模組引數列表之外
endmodule

[USF-XSim 62] ‘compile’ step failed with error(s) while executing ‘D:/vivado/LED_8light/LED_8light.sim/sim_1/behav/compile.bat’ script. Please check that the file has the correct ‘read/write/execute’ permissions and the Tcl console output for any other possible errors or warnings.

在input中使用reg

module ALU(
    input reg y
    );
endmodule

[USF-XSim-62] ‘compile’ step failed with error(s) while executing ‘D:/vivado/SinglePeriodCPU/SinglePeriodCPU.sim/sim_1/behav/compile.bat’ script. Please check that the file has the correct ‘read/write/execute’ permissions and the Tcl console output for any other possible errors or warnings.

elaborate error類

引數名字不符

module clock_div(
    input clk,
    output reg clk_div = 0
    );
    // 函式定義
endmodule

// 錯誤呼叫
clock_div U1(
    .clock(clock), // 引數名應為clk，而不是clock
    .clk_div(clk_sys)
);

[USF-XSim-62] ‘elaborate’ step failed with error(s). Please check the Tcl console output or ‘D:/vivado/LED_8light/LED_8light.sim/sim_1/behav/elaborate.log’ file for more information.

匿名的元件呼叫

// 禁止匿名呼叫，應該為
// clock_div U1 (
clock_div ( 
    .clk(clock),
    .clk_div(clk_sys)
);

[USF-XSim-62] ‘elaborate’ step failed with error(s). Please check the Tcl console output or ‘D:/vivado/LED_8light/LED_8light.sim/sim_1/behav/elaborate.log’ file for more information.
[VRFC 10-1047] module instantiation should have an instance name [“D:/vivado/SinglePeriodCPU/SinglePeriodCPU.srcs/sources_1/new/CPU.v”:95]

傳入reg變數給reg引數

// 模組
module led_8lights(
    input clock,
    input reset,
    output reg [7:0] Y
    );
    // 模組內容
endmodule

// 呼叫
reg [7:0] Y;  // 錯誤
wire [7:0] Y; // 正確
led_8lights uut(
    .clock(clock),
    .reset(reset),
    .Y(Y)
);

[VRFC 10-529] concurrent assignment to a non-net Y is not permitted [“D:/vivado/LED_8light/LED_8light.srcs/sim_1/new/led_sim.v”:56]