Modelsim自動化仿真之do文件書寫
阿新 • • 發佈：2018-09-03
-a 信號 art ipc tar and mode ati flag
do 文件書寫
創建本地庫
vlib ./work
You must use vlib rather than operating system commands to creat a library directory or index file.映射邏輯庫到物理目錄
vmap work ./work
編譯源代碼（缺省編譯到 work 本地庫）
vlog ./../design/*.v
vlog ./tb_div_odd.v
可以使用 "- work" 指定編譯到哪個庫中啟動仿真器
vsim -voptargs=+acc work.tb_div_odd
添加波形
add wave tb_div_odd/*
執行仿真
run -all
示例 run.do 文件如下所示：
# 退出當前仿真 quit -sim # 清輸出窗口 .main clear # 創建本地庫 # You must use vlib rather than operating system commands to creat a library directory or index file. vlib ./work vlib ./altera_lib # 將邏輯庫名映射庫路徑 vmap work ./work vmap alt_lib ./altera_lib # 編譯 verilog 源代碼 # 其中的 "- work" 參數用來具體指定將 verilog 源代碼編譯到哪個庫中，缺省編譯到 work 庫 vlog -work alt_lib ./altera_mf.v vlog -work alt_lib ./../quartus_prj/ipcore_dir/pll_1.v vlog -work work ./../design/*.v vlog -work work ./tb_ipcore_pll.v # 啟動仿真器 vsim -voptargs=+acc -L alt_lib -L work work.tb_ipcore_pll # 添加波形 add wave tb_ipcore_pll/* # 執行仿真 run 1us
參考 run.do 文件如下所示：
vsim -t ns -voptargs=+acc -L design -L base_space base_space.*.v # -t 運行仿真的精度是ns # -L 鏈接庫關鍵字 ======================================================================== 虛擬信號 #前面數字書寫默認為10進制 virtual type { {01 IDLE} {02 A} {04 B} {08 C} {16 D} {32 E} } vir_new_signal virtual function { (vir_new_signal)tb_seq_det/seq_det_inst/state } new_state add wave tb_seq_det/seq_det_inst/new_state ======================================================================== quit -sim .main clear vlib ./lib/ vlib ./lib/work/ vmap work ./lib/work/ vlog -work work ./tb_shift_reg.v vlog -work work ./../design/shift_reg.v vsim -voptargs=+acc work.tb_shift_reg add wave tb_shift_reg/clk add wave tb_shift_reg/rst_n add wave tb_shift_reg/mem1x16 add wave tb_shift_reg/i_30 add wave tb_shift_reg/i_data add wave tb_shift_reg/shift_reg_inst/shift_reg add wave tb_shift_reg/shift_reg_inst/s_cnt add wave tb_shift_reg/shift_reg_inst/s_flag add wave tb_shift_reg/shift_reg_inst/s_flag_delay add wave tb_shift_reg/shift_reg_inst/o_data add wave tb_shift_reg/o_data run 10us ========================================================================== virtual.do virtual type { {0x1 IDLE}{0x2 A}{0x4 B}{0x8 C}{0x10 D}{0x20 E}} vir_new_signal virtual function -install /tb_seq_det/seq_det_inst -env /tb_seq_det { (vir_new_signal)tb_seq_det/seq_det_inst/state} new_state ========================================================================== 後仿真 quit -sim .main clear vlib ./lib/ vlib ./lib/work/ vlib ./lib/altera_lib/ vmap work ./lib/work/ vmap altera_lib ./lib/altera_lib/ vlog -work work ./tb_seq_det.v vlog -work work ./../design/*.vo vlog -work altera_lib ./altera_lib/*.v vsim -t ns -sdfmax tb_seq_det/seq_det_inst=seq_det_v.sdo -voptargs=+acc -L altera_lib work.tb_seq_det add wave tb_seq_det/* run 10us
Modelsim自動化仿真之do文件書寫