韌體庫FSMC_NORSRAMInit( )函式程式碼分析
阿新 • • 發佈：2018-11-17
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相關結構體
typedef struct { uint32_t FSMC_Bank; //指定FSMC NOR/SRAM的儲存區 塊一的1~4區 uint32_t FSMC_DataAddressMux; //資料地址匯流排複用位設定 uint32_t FSMC_MemoryType; //儲存器型別定義 uint32_t FSMC_MemoryDataWidth; //資料匯流排寬度 uint32_t FSMC_BurstAccessMode; //成組模式使能設定 uint32_t FSMC_AsynchronousWait; //手冊中這一位保留 uint32_t FSMC_WaitSignalPolarity; //設定儲存器產生的等待訊號的極性 uint32_t FSMC_WrapMode; //支援非對齊的成組模式 uint32_t FSMC_WaitSignalActive; //配置等待時序 uint32_t FSMC_WriteOperation; //寫使能 uint32_t FSMC_WaitSignal; //等待模式使能 uint32_t FSMC_ExtendedMode; //擴充套件模式使能 uint32_t FSMC_WriteBurst; //成組寫使能位 FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; //BTRx FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; //BWTRx }FSMC_NORSRAMInitTypeDef;
typedef struct { uint32_t FSMC_AddressSetupTime; //地址建立時間 0~F uint32_t FSMC_AddressHoldTime; //地址保持時間 0~F uint32_t FSMC_DataSetupTime; //資料保持時間 0~FF uint32_t FSMC_BusTurnAroundDuration; //匯流排恢復時間 0~F uint32_t FSMC_CLKDivision; //時鐘分頻比(CLK訊號) uint32_t FSMC_DataLatency; //(同步成組式NOR快閃記憶體的)資料保持時間 uint32_t FSMC_AccessMode; //訪問模式 }FSMC_NORSRAMTimingInitTypeDef;
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相關引數的結構體及巨集定義
/**************FSMC_NORSRAMInit()函式結構體引數***********************/ /*FSMC_Bank bank1 區位暫存器選擇引數*/ typedef struct { __IO uint32_t BTCR[8]; } FSMC_Bank1_TypeDef; /*偏移 暫存器名稱 復位值 說明 000h FSMC_BCR1 0x000030DB SRAM/NOR快閃記憶體片選控制暫存器 1 004h FSMC_BTR1 0x0FFFFFFF SRAM/NOR快閃記憶體片選時序暫存器 1 008h FSMC_BCR2 0x000030D2 SRAM/NOR快閃記憶體片選控制暫存器 2 00Ch FSMC_BTR2 0x0FFFFFFF SRAM/NOR快閃記憶體片選時序暫存器 2 010h FSMC_BCR3 0x000030D2 SRAM/NOR快閃記憶體片選控制暫存器 3 014h FSMC_BTR3 0x0FFFFFFF SRAM/NOR快閃記憶體片選時序暫存器 3 018h FSMC_BCR4 0x000030D2 SRAM/NOR快閃記憶體片選控制暫存器 4 01Ch FSMC_BTR4 0x0FFFFFFF SRAM/NOR快閃記憶體片選時序暫存器 4*/ #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) /*FSMC_DataAddressMux 地址資料複用使能引數相關定義*/ #define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) #define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) #define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ ((MUX) == FSMC_DataAddressMux_Enable)) /*FSMC_MemoryType 控制記憶體型別選擇引數相關定義*/ #define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) #define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) #define FSMC_MemoryType_NOR ((uint32_t)0x00000008) #define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ ((MEMORY) == FSMC_MemoryType_NOR)) /*FSMC_MemoryDataWidth 資料匯流排寬度相關引數定義*/ #define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) #define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) #define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ ((WIDTH) == FSMC_MemoryDataWidth_16b)) /*FSMC_BurstAccessMode 成組模式使能位相關引數定義*/ #define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) #define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) #define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ ((STATE) == FSMC_BurstAccessMode_Enable)) /*FSMC_WaitSignalPolarity 等待訊號極性控制相關引數定義*/ #define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) #define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) #define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ ((POLARITY) == FSMC_WaitSignalPolarity_High)) /*FSMC_WrapMode 非對其成組模式設定相關引數定義*/ #define FSMC_WrapMode_Disable ((uint32_t)0x00000000) #define FSMC_WrapMode_Enable ((uint32_t)0x00000400) #define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ ((MODE) == FSMC_WrapMode_Enable)) /*FSMC_WaitSignalActive 配置等待時序相關引數定義*/ #define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) #define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) #define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) /*FSMC_WriteOperation 寫使能位相關引數定義*/ #define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) #define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) #define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ ((OPERATION) == FSMC_WriteOperation_Enable)) /*FSMC_WaitSignal 等待使能位設定相關引數定義*/ #define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) #define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) #define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ ((SIGNAL) == FSMC_WaitSignal_Enable)) /*FSMC_ExtendedMode 擴充套件模式使能相關引數定義*/ #define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) #define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) #define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ ((MODE) == FSMC_ExtendedMode_Enable)) /*FSMC_WriteBurst 成組寫使能位相關引數設定*/ #define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) #define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) #define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ ((BURST) == FSMC_WriteBurst_Enable)) /*地址建立時間*/ #define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) /*地址保持時間*/ #define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) /*資料保持時間*/ #define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) /*匯流排恢復時間*/ #define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) /*時鐘分頻比(CLK訊號)*/ #define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) /*(同步成組式NOR快閃記憶體的)資料保持時間*/ #define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) /*訪問模式 (Access mode)*/ #define FSMC_AccessMode_A ((uint32_t)0x00000000) #define FSMC_AccessMode_B ((uint32_t)0x10000000) #define FSMC_AccessMode_C ((uint32_t)0x20000000) #define FSMC_AccessMode_D ((uint32_t)0x30000000) #define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ ((MODE) == FSMC_AccessMode_B) || \ ((MODE) == FSMC_AccessMode_C) || \ ((MODE) == FSMC_AccessMode_D))
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函式體
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
{
/* 檢查引數*/
assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
/*Bank1 NOR / SRAM 控制暫存器配置 BCRx */
/*根據FSMC_NORSRAMInitStruct->FSMC_Bank的值選擇相應區的控制暫存器*/
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | /*資料地址匯流排複用設定 BCRx 1 */
FSMC_NORSRAMInitStruct->FSMC_MemoryType | /*控制記憶體型別設定 BCRx 3：2*/
FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | /*選擇資料匯流排寬度 BCRx 5：4*/
FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | /*設定成組模式使能位 BCRx 8*/
FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait | /*手冊中這一位保留*/
FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | /*設定儲存器產生的等待訊號的極性 BCRx 9*/
FSMC_NORSRAMInitStruct->FSMC_WrapMode | /*支援非對齊的成組模式 BCRx 10*/
FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | /*配置等待時序 BCRx 11*/
FSMC_NORSRAMInitStruct->FSMC_WriteOperation | /*寫使能 BCRx 12*/
FSMC_NORSRAMInitStruct->FSMC_WaitSignal | /*成組模式下等待使能位設定 BCRx 13*/
FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | /*擴充套件模式使能設定 BCRx 14*/
FSMC_NORSRAMInitStruct->FSMC_WriteBurst; /*成組寫使能位相關引數設定 BCRx 19*/
/*如果是NOR快閃記憶體 使能記憶體訪問使能位 BCRx 6*/
if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
{
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
}
/* Bank1 NOR/SRAM 時序暫存器配置 BTRx */
/*根據FSMC_NORSRAMInitStruct->FSMC_Bank的值選擇相應區的時序暫存器*/
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | /*地址建立時間*/
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | /*地址保持時間*/
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | /*資料保持時間*/
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | /*匯流排恢復時間*/
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | /*時鐘分頻比*/
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | /*(同步成組式NOR快閃記憶體的)資料保持時間*/
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; /*訪問模式*/
/* 如果使用 BWTRx 暫存器 */
if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
{
/*檢查引數*/
assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
/*設定同上*/
FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
}
else
{
/*若沒有用 BWTRx 復位暫存器 復位值 0X 0FFF FFFF*/
FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
}
}