2. 程式人生 > >AR# 71416 ZynqMP: How to get baremetal DPDMA example to work with single lane DisplayPort configured

AR# 71416 ZynqMP: How to get baremetal DPDMA example to work with single lane DisplayPort configured

阿新 • • 發佈：2018-11-30

https://www.xilinx.com/support/answers/71416.html

Description

On a Zynq UltraScale+ MPSoC device how can I get the bare metal DPDMA example to work with single lane DisplayPort configured.

Solution

Below are the steps you need to follow.

  1. Create a standalone BSP project using ZCU102 HDF and then change the psu_dp to dppsu as mentioned in the wiki
    http://www.wiki.xilinx.com/ZynqMP+Standalone+DisplayPort+Driver     Test Procedure section.
    By default, psu_dp is set to avbuf by the SDK.



  2. Open the MSS file and then export the DPDMA example.




  3. Import the DPDMA example files.

  4. In xdpdma_video_example.c, modify RunCfgPtr->LaneCount to 'LANE_COUNT_1' and  RunCfgPtr->UseMaxLaneCount to '0' as shown below. 


  5. In xdppsu.c, xpdpsu_hw.h, and xavbuf_clk.c, modify the code as shown below.
    Note: changes to xavbuf_clk.c are required for the 2018.1 release only and this patch is merged into the 2018.2 release.






  6. Build the project, and once the build is completed, create a BOOT.bin using the FSBL, PMUFW and DPDMA example elf.
  7. Run targetting a ZCU102 connected with DisplayPort.
    You should now see a green color on the bottom half of the DisplayPort monitor:
    .

  8. Target console log:
Xilinx Zynq MP First Stage Boot Loader Release 2018.1   Aug  6 2018  -  10:19:50 DPDMA Generic Video Example Test HPD event .......... ! Connected. Lane count =    1 Link rate =     20
Starting Training...         ! Training succeeded. DONE! .......... HPD event Generating Overlay..... Successfully ran DPDMA Video Example Test ![在這裡插入圖片描述](https://www.xilinx.com/content/dam/xilinx/Image/DPDMA1_201808101028003425.png) ![在這裡插入圖片描述](https://www.xilinx.com/content/dam/xilinx/Image/DPDMA2_201808101028212933.png) ![在這裡插入圖片描述](https://www.xilinx.com/content/dam/xilinx/Image/DPDMA3_201808101028366749.png) ![在這裡插入圖片描述](https://www.xilinx.com/content/dam/xilinx/Image/DPDMA4_201808101046104278.png) ![在這裡插入圖片描述](https://www.xilinx.com/content/dam/xilinx/Image/DPDMA5_201808101052462082.png) ![在這裡插入圖片描述](https://www.xilinx.com/content/dam/xilinx/Image/DPDMA6_201808101053043116.png) ![在這裡插入圖片描述](https://www.xilinx.com/content/dam/xilinx/Image/DPDMA7_201808101053231792.png) ![在這裡插入圖片描述](https://www.xilinx.com/content/dam/xilinx/Image/DPDMA8_201808101058200186.png)

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