Chisel3 - 運算子和位寬推斷

阿新 • • 發佈：2018-12-02

https://mp.weixin.qq.com/s/rI-CJM6GyI6EUHPZ3uYiFg

如同Verilog中的眾多運算子，Chisel也針對自身的資料型別，提供了很多運算子。 Chisel語言內嵌於Scala。在Scala中，基本上所有的運算子都被當做一般的字元，可以作為命名符號（identifier）的一部分。並且Scala支援省略函式呼叫時，括在引數兩邊的括號。所以Scala中定義運算子過載很簡單，可以很大的提高程式碼的可讀性。 1. 運算子參考連結：

https://github.com/freechipsproject/chisel3/wiki/Builtin-Operators a. Bitwise operators

~ & | ^ 這些其實都是方法名，如：

b. Bitwise reductions

c. Equality comparison.

d. Shifts

e. Bitfield manipulation

f. Logical Operations

g. Arithmetic operations

h. Arithmetic comparisons

2. 位寬推斷兩個相同型別但位寬不同的變數，也可以進行運算。運算引數以及運算結果的位寬會進行自動推斷拓展。

參考連結： https://github.com/freechipsproject/chisel3/wiki/Width-Inference

Chisel provides bit width inference to reduce design effort. Users are encouraged to manually specify widths of ports and registers to prevent any surprises, but otherwise unspecified widths will be inferred by the Firrtl compiler. For all circuit components declared with unspecified widths, the FIRRTL compiler will infer the minimum possible width that maintains the legality of all its incoming connections. Implicit here is that inference is done in a right to left fashion in the sense of an assignment statement in chisel, i.e. from the left hand side from the right hand side. If a component has no incoming connections, and the width is unspecified, then an error is thrown to indicate that the width could not be inferred. For module input ports with unspecified widths, the inferred width is the minimum possible width that maintains the legality of all incoming connections to all instantiations of the module. The width of a ground-typed multiplexor expression is the maximum of its two corresponding input widths. For multiplexing aggregate-typed expressions, the resulting widths of each leaf subelement is the maximum of its corresponding two input leaf subelement widths. The width of a conditionally valid expression is the width of its input expression. For the full formal description see the Firrtl Spec.

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