module cy4(input[3:0] a,b,c,d, 
           input vld_in,//輸入有效指示訊號
		   input clk,rst_n,
		   output reg[15:0] dout,
		   output reg[7:0] s1,
		   output reg[7:0] s2,
		   output reg vld_out//輸出有效指示訊號
		   );
		   
reg vld_in_ff0;//中間快取暫存器

always  @(posedge clk or negedge rst_n)
    if(rst_n == 1'b0) s1 <= 0;
	else s1 <= a * b;
	
always  @(posedge clk or negedge rst_n)
    if(rst_n == 1'b0) s2 <= 0;
	else s2 <= c * d;

always  @(posedge clk or negedge rst_n)
    if(rst_n == 1'b0) dout <= 0;
	else dout <= s1 * s2;
	
always  @(posedge clk or negedge rst_n)
    if(rst_n == 1'b0) vld_in_ff0 <= 0;
	else  vld_in_ff0  <= vld_in;
	
always  @(posedge clk or negedge rst_n)
    if(rst_n == 1'b0) vld_out <= 0;
	else vld_out  <= vld_in_ff0;
endmodule
 

如圖，兩個暫存器之間只有一個乘法器。