RISC-V 雙週簡報 (2018-08-03)

要點新聞：

• RISC-V Tokyo Day 2018徵集演講即將截止！
• 印度Shakti處理器流片成功併成功Boot起Linux

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Is open source silicon the next logical step after the proprietary IP licensing model? To paraphrase Sir Robin Saxby, founding CEO of ARM, at the 2013 Global Semiconductor Alliance Entrepreneurship Conference in London: “Don’t try and build the next ARM; build the company that will replace ARM.”

注：Sir Robin Saxby是ARM的首位CEO，也是IP商業授權模式的開創者。

RISC-V Day Tokyo 會議徵稿

2018年10月18日, RISC-V Day Tokyo將在Keio University舉辦，演講徵集即將結束。

頭條

印度首個可執行Linux的RISC-V微處理器晶片成功啟動Linux

印度自研的Shakti處理器最近成功流片並且啟動Linux。

這顆測試樣片採用的是其C-Class處理器。

在YC網站上，有人貼出了InCore的創始人和CEO G S Madhusudan對於Shakti的一些個人看法:

As the lead architect of Shakti and the guy who helped kick-start the project, I figure I am owed my 2 cents !

1. We never positioned it as an ARM killer ! That was the imagination of the reporter who wrote the article.
2. Shakti is not a state only project. Parts of Shakti are funded by the govt, these relate to cores and SoCs needed by the Govt. The defense and strategic sector procurement is huge, runs in the 10s of billions of USD.There is significant funding in terms of manpower, tools and free foundry shuttles provided by the private sector. In fact Shakti has more traction with the private sector than the govt sector in terms of immediate deployments.
3. The CPU eco-system including ARM’s is a bit sclerotic. It is not the lic cost that is the problem, it is the inherent lack of flexibility in the model.
4. Shakti is not only a CPU. Other components include a new interconnect based on SRIO, GenZ with our extensions accompanied by open source silicon, a new NVMe+ based storage standard again based on open source SSD controller silicon (using Shakti cores of course), open source Rust based MK OS for supporting tagged ISAs for secure Shakti variants, fault tolerant variants for aerospace and ADAS applications, ML/AI accelerators based on our AI research (we are one of the top RL ML labs around). 5 the Shakti program will also deliver a whole host of IPs including the smaller trivial ones and also as needed bigger blocks like SRIO, PCIe and DDR4. All open source of course.
5. We are also doing our own 10G and 25G PHYs
6. A few startups will come out of this but that can wait till we have a good open source base.
7. The standard cores coming out of IIT will be production grade and not research chips.

And building a processor is still tough these days. Try building a 16 core, quad wide server monster with 4 DDR4 channels, 4x25G I/O ports, 2 ports for multi-socket support. All connected via a power optimized mesh fabric. Of course you have to develop the on-chip and off-chip cache coherency stuff too ! 8. And yes we are in talks with AMD for using the EPYC socket. But don’t think they will bite.

Just ignore the India bit and look at what Shakti aims to achieve, then you will get a better picture. I have no idea how successful we will be and I frankly do not care. What we will achieve (and have to some extent already) is - create a critical mass of CPU architects in India - create a concept to fab eco-system ind India for designing any class of CPUs - add a good dose of practical CPU design knowhow into the engineering curriculum - become one of the top 5 CPU arch labs around

Shakti is already going into production. The first design is actually in the control system of an experimental civilian nuclear reactor. IIT is within the fallout zone so you can be sure we will get the design right. If you want any further info, mail me. My email is on the Shakti site. G S Madhusudan

而在YC論壇上，有人又隨後比較了中國和印度的半導體行業：

Very different things are in Indian semiconductor industry in comparison to China:

Availability of professionals

• India: makes tons of electronics engineers and semi specialists, but very very few of them find employment in the country.
• China: there is a somewhat ok amount of undergraduate cadres, but for anything above this, you have to attract people from abroad. And yes, Chinese fabless were hiring from abroad since the very beginning. In fact, people who make SoCs at Allwinner, Rockchip and etc are around 50% undergrad and 50% masters level people. In their early days they were eager to hire random college grads and teach them verilog on site.

Goals

• India: a research program, all work in the past few decades was about delivering some kind of proof of concept level “national chip”
• China: make money quick - 9 out of 10 Chinese fabless start with bog down standard, off the shelf “solutions” from ARM, and add some flavour: here you have 4 channel camera controller, here eDP on chip, and here 10G Ethernet for pennies.

Markets

• India: with all respect, the truth is there are none. And from many people I hear the same criticism - even if the 10th in a row state backed effort to make the “national chip” will succeed, there will be no chances of it ever sustaining it with microscopic domestic market as demanded by political mandate.
• China: foreign markets - even 15 years ago, Chinese fabless well understood that their value proposition is actually lesser in domestic market than for the export manufacturing. Most Chinese buying a PC 20 years ago were not deliberating whether their PC has Sigmatel audio codec or some cheaper domestic analogue, but for somebody making stuff for export, every penny saved on expensive imported chip mattered a lot. Even today, the pattern holds: Chines domestic market smartphone models have high-end Qualcomm or Samsung flagship class chips in their majority, and for export they do Mediatek, Allwinner, and Spreadtrum

Links:

點評：如何看待Shakti

當看到印度的這顆處理器的時候，我能夠聽到不少羨慕印度政府能夠支援RISC-V的聲音，與此同時前段時間上海也釋出了RISC-V響應的政策。我的幾個觀點如下：

1. 做好自己的事情，無需羨慕其他人，我們做的並不差。市場和客戶的需求才是最重要的，企業的盈利和生存才是最重要的。
2. RISC-V在中國大陸發展最大一個特點就是企業參與的數量和投入遠遠超過科研院所，我認為這是不能再好的情況。因為企業最貼近市場，從資源配置的角度執行效率是最高的，在這一點上，我們的起步真的很好。
3. 政府的力量當然不可或缺，但是我們能夠看到上海市的政策更多的是幫助企業衝刺產業化的最後一關，政府更希望企業自己找到方向，而非過多的指手畫腳。要知道企業的成功，企業家精神是不可或缺的。

郭雄飛

簡訊快訊

技術討論

為什麼需要MPIE (Why MPIE)

Pierre G.在RISC-V ISA Dev提出為什麼RISC_V需要要MPIE Pierre G.說理解SPIE & UPIE的作用，但是risc-v進入"machine mode"模式沒法再通過中斷進入更低級別的 的特權模式，那為什麼需要MPIE?

I have a naive question : why do we need MPIE ? I understand how it works : when an interrupt is taken, MPIE captures the value of MIE, and at the end on the interrupt routine, MRET will copy back MPIE within MIE.

But, in anycase MPIE is necessarily equals to 1 :

• if an interrupt is taken, this means that MIE was enabled.
• at the time the interrupt occurs, MIE is copied into MPIE; so is 1.
• MIE is written to 0 After the first interrupt will be serviced (execution of MRET), MPIE still holds 1, and MIE is restored using MPIE=1.

I understand the role of SPIE & UPIE because S&U mode can be interrupted to go into machine mode, but I do not understand the need of MIPE since machine mode cannot be interrupted and switch to lower priority mode.

Allen Baum給出了原因，MPIE是為了防止或者允許重入, Allen Baum的具體解釋是:

Obviously, M-mode only implementations are allowed, so you need to be able to take interrupts from m-mode to m-mode. When you first enter M-mode, interrupts are disabled, and you need to explicitly save state and reenable interrupts in order to take another interrupt (unless M-mode knows there is no state to save, but that only works once…).

Taking exceptions (synchronous exceptions) is nastier - your handler M-mode code should be written so that it doesn’t take an exception, or at least not before its had time to save a few CSRs somewhere (e.g. saving the few csrs better not trao!). Primarily, that means access to the physical address of the handler should guaranteed, and access to the save area should be guaranteed. Having said that, it is still the case that an NMI could come in - that’s basically fatal in this scenario, and should be confined to HW error conditions that are fatal anyway.

Getting back to the original question: the reason you need MPIE is to prevent and allow reentrance.

Jacob Bachmeyer對Allen Baum的答案做了進一步的詮釋， 對於 “Taking exceptions (synchronous exceptions)…and access to the save area should be guaranteed.”， Jacob Bachmeyer補充說

This was hashed out previously in the “nested trap” discussions: all trap handlers must have a context-save area that can be accessed without incurring a horizontal trap. This issue also hits the supervisor. It is more than just the CSRs: the entire general register file must be saved.

對於"Having said that, … that are fatal anyway", Jacob Bachmeyer補充說

Does this mean that MPIE in the NMI handler is effectively the “recoverable NMI” flag? If MPIE is set when the NMI handler is entered, nothing has been lost (since the monitor was prepared for an interrupt) and the monitor can resume execution after handling the NMI, probably after software-delegating the NMI to a “machine check” handler previously registered by the supervisor using some to-be-defined SBI call. If MPIE is clear when the NMI handler is entered, the NMI occurred while entering the monitor trap handler and the resume point has been destroyed; the only path forwards is to reset.

High-reliability system can avoid these problems by placing the monitor entry point and context save areas in internal (multi-port) SRAM, with extensive ECC on that SRAM and dedicated ECC scrubbing hardware with its own SRAM port. (If that fails, the main registers probably cannot be trusted to hold values either and the system will crash no matter what.)

在原文還有很多設計M-mode和特權模式相關的精彩討論.

安全點評

NXP將使用Dover Microsystems的CoreGuard技術

NXP 和 Dover Microsystems 在2018年7月23日發表聯合宣告。NXP將在其處理器中使用 Dover Microsystems 的 CoreGuard 技術來鞏固其安全處理器。面對物聯網和端計算快速增長的需求，NXP將致力於提供全面的安全保護來應對從物理層、邏輯層和網路層的攻擊。Dover Microsystems 的 CoreGuard 技術提供了一種全新的方式來保護處理器。通過使用預先確立的規則，CoreGuard 實時檢測處理器上執行的每一條指令，在惡意指令執行的第一時間將其阻截。

編輯注：Dover Microsystems 是美國MIT Draper實驗室孵化的初創企業。CoreGuard實際上來源於美國DARPA的CRASH專案，旨在研究創新性的能從根本上保證計算安全的新技術。Draper實驗室提出了使用generic tag來標註計算系統中的資料和指令，並通過tag協處理器來實時監測指令執行的安全性。具體的資訊，可參見：

• NXP and Dover Microsystems Join Forces to Deliver Unprecedented Network Security, Safety, and Privacy for Processors Link
• Udit Dhawan, et al. “Architectural support for software-defined metadata processing.” In proc. of the International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 487-502, 2015. DOI
• Udit Dhawan, et al. “PUMP: A programmable unit for metadata processing.” In proc. of the Workshop on Hardware and Architectural Support for Security and Privacy, 2014. DOI

行業視角

IEEE Specturm: RISC-V’s Open-Source Architecture Shakes Up Chip Design

Stacey Higginbotham在IEEE Specturm雜誌八月刊發表了文章"The Rise of RISC"。

This technology lowers the cost of creating custom chips, which means more and more companies may elect to build their own. As for the existing players, I don’t think RISC-V represents a bigger threat to Intel than does the slow fade of Moore’s Law and former customers deciding to build their own dedicated silicon. And I don’t think Arm will necessarily lose licensing fees to RISC-V right away—but the technology could bring on a wave of competitive silicon that hurts incumbents in the long run.

芯來科技創始人胡振波專訪

蜂鳥的架構師以及芯來科技的創始人胡振波接受了半導體行業觀察的專訪。胡大大從多個角度分享了他對RISC-V的看法，不要錯過。

市場相關

Dolphin Integration的支援RISC-V的IDE: SmartVison™ 2.4.0

Dolphin釋出了最新的IDE: SmartVison™ 2.4.0，對RISC-V的支援更加成熟和完善。

一些新特性：

• Support of the “F” instruction set extension for single precision floating point registers and operations
• New stack-unwinding tool in the debug toolbox to speed-up application program debug by giving access to program execution stack frames
• Several new pre-defined MCU subsystems based on the RV32 Tornado both in simulation and emulation for reducing application development time and for easily use RISC-V peripherals
• FreeRTOS support for RV32 Tornado to debug efficiently RTOS-based applications
• New intuitive wizard for the creation of RISC-V subsystem projects and the generation of RTL configuration files

暴走事件

2018年8月

• 2018年8月16日在寧夏大學舉辦的計算機工程與工藝學術年會及第八屆“微處理器論壇”中，會有一場關於“RISC-V開放指令集和其硬軟體生態”的大會報告。

2018年10月

• 2018年10月18日, RISC-V Day Tokyo將在Keio University舉辦，演講徵集已經開始。註冊網站

2018年12月

招聘簡訊

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整理編集: 宋威、黃柏瑋、汪平、林容威、傅煒、巍巍、郭雄飛、黃瑋

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