1.S5PV210定時器系統概述和時鐘結構框圖分析
阿新 • • 發佈：2019-01-09
PULSE WIDTH MODULATION TIMER（脈衝寬度調製定時器）
1.1 OVERVIEW OF PULSE WIDTH MODULATION TIMER
The S5PV210 has five 32-bit Pulse Width Modulation (PWM) timers. These timers generate internal interrupts for the ARM subsystem. In addition, Timers 0, 1, 2 and 3 include a PWM function, which drives an external I/O signal.The PWM in timer 0 has an optional dead-zone generator capability to support a large current device. Timer 4 is internal timers without output pins.
S5PV210有5個32位脈衝寬度調製定時器。這些定時器能夠為ARM系統產生內部中斷。此外，定時器0/1/2/3包含一個PWM功能，並且能產生外部的I/O訊號。PWM定時器0還包含一個可選的死區生成器功能來支援一個大電流裝置。定時器4是內部定時器，沒有外部i/o引腳。
The Timers use the APB-PCLK as source clock. Timers 0 and 1 share a programmable 8-bit prescaler that
provides the first level of division for the PCLK. Timers 2, 3, and 4 share a different 8-bit prescaler. Each timer hasits own private clock-divider that provides a second level of clock division (prescaler divided by 2, 4, 8, or 16).Alternatively, the timers can select a clock source from CMU. Timers 0, 1, 2, 3, and 4 select SCLK_PWM.
這些定時器使用APB總線上的PCLK作為時鐘源。定時器0和1共用一個8位的可程式設計預分頻器來為PCLK進行一級分頻。定時器2/3/4共用另一個8位的預分頻器。每一個定時器都有它自己的二級時鐘分頻器（分頻係數為2/4/8/16）。或者，定時器也能選擇從CMU作為一個時鐘源，定時器0/1/2/3/4選擇SCLK_PWM作為時鐘訊號。
Each timer has its own 32-bit down-counter which is driven by the timer clock. The down-counter is initially loaded from the Timer Count Buffer register (TCNTBn). If the down-counter reaches zero, the timer interrupt request is
generated to inform the CPU that the timer operation is complete. If the timer down-counter reaches zero, the value of corresponding TCNTBn automatically reloads into the down-counter to start a next cycle. However, if the timer stops, for example, by clearing the timer enable bit of TCONn during the timer running mode, the value of TCNTBn is not reloaded into the counter.
每一個定時器都有它們自己的通過定時器時鐘驅動的向下計數器。向下計數器的初值從TCNTBn計數器讀取。如果向下計數器減到0後，就會產生一個定時器中斷請求來通知CPU定時器操作完成。如果定時器向下計數器減到0，相應的TCNTBn的值將會自動裝載到向下計數器然後開始下一個迴圈。然而，如果定時器停止，例如在定時器工作時通過清除TCONn暫存器中的定時器使能位，那麼TCNTBn中的值就不會被過載到計數器中。
The PWM function uses the value of the TCMPBn register. The timer control logic changes the output level if down-counter value matches the value of the compare register in timer control logic. Therefore, the compare register determines the turn-on time (or turn-off time) of a PWM output.
PWM功能使用TCMPBn暫存器的值。如果在定時器控制邏輯中向下計數器的值與比較暫存器的值相匹配，那麼定時器控制邏輯改變輸出電平。因此，比較暫存器決定開啟或者關閉定時器的PWM輸出。
The TCNTBn and TCMPBn registers are double buffered to allow the timer parameters to be updated in the middle of a cycle. The new values do not take effect until the current timer cycle completes.
1.1 OVERVIEW OF PULSE WIDTH MODULATION TIMER
The S5PV210 has five 32-bit Pulse Width Modulation (PWM) timers. These timers generate internal interrupts for the ARM subsystem. In addition, Timers 0, 1, 2 and 3 include a PWM function, which drives an external I/O signal.The PWM in timer 0 has an optional dead-zone generator capability to support a large current device. Timer 4 is internal timers without output pins.
S5PV210有5個32位脈衝寬度調製定時器。這些定時器能夠為ARM系統產生內部中斷。此外，定時器0/1/2/3包含一個PWM功能，並且能產生外部的I/O訊號。PWM定時器0還包含一個可選的死區生成器功能來支援一個大電流裝置。定時器4是內部定時器，沒有外部i/o引腳。
The Timers use the APB-PCLK as source clock. Timers 0 and 1 share a programmable 8-bit prescaler that
provides the first level of division for the PCLK. Timers 2, 3, and 4 share a different 8-bit prescaler. Each timer hasits own private clock-divider that provides a second level of clock division (prescaler divided by 2, 4, 8, or 16).Alternatively, the timers can select a clock source from CMU. Timers 0, 1, 2, 3, and 4 select SCLK_PWM.
這些定時器使用APB總線上的PCLK作為時鐘源。定時器0和1共用一個8位的可程式設計預分頻器來為PCLK進行一級分頻。定時器2/3/4共用另一個8位的預分頻器。每一個定時器都有它自己的二級時鐘分頻器（分頻係數為2/4/8/16）。或者，定時器也能選擇從CMU作為一個時鐘源，定時器0/1/2/3/4選擇SCLK_PWM作為時鐘訊號。
Each timer has its own 32-bit down-counter which is driven by the timer clock. The down-counter is initially loaded from the Timer Count Buffer register (TCNTBn). If the down-counter reaches zero, the timer interrupt request is
generated to inform the CPU that the timer operation is complete. If the timer down-counter reaches zero, the value of corresponding TCNTBn automatically reloads into the down-counter to start a next cycle. However, if the timer stops, for example, by clearing the timer enable bit of TCONn during the timer running mode, the value of TCNTBn is not reloaded into the counter.
每一個定時器都有它們自己的通過定時器時鐘驅動的向下計數器。向下計數器的初值從TCNTBn計數器讀取。如果向下計數器減到0後，就會產生一個定時器中斷請求來通知CPU定時器操作完成。如果定時器向下計數器減到0，相應的TCNTBn的值將會自動裝載到向下計數器然後開始下一個迴圈。然而，如果定時器停止，例如在定時器工作時通過清除TCONn暫存器中的定時器使能位，那麼TCNTBn中的值就不會被過載到計數器中。
The PWM function uses the value of the TCMPBn register. The timer control logic changes the output level if down-counter value matches the value of the compare register in timer control logic. Therefore, the compare register determines the turn-on time (or turn-off time) of a PWM output.
PWM功能使用TCMPBn暫存器的值。如果在定時器控制邏輯中向下計數器的值與比較暫存器的值相匹配，那麼定時器控制邏輯改變輸出電平。因此，比較暫存器決定開啟或者關閉定時器的PWM輸出。
The TCNTBn and TCMPBn registers are double buffered to allow the timer parameters to be updated in the middle of a cycle. The new values do not take effect until the current timer cycle completes.