verilog之8位二進位制乘法
阿新 • • 發佈:2019-02-14
兩個8位二進位制數a,b,c=a*b;將輸入a,b和結果c顯示到七段管上,用十六進位制表示,a用兩個七段管,b用兩個七段管,c用四個七段管
module mutiple(a,b,outa1,outa2,outb1,outb2,out1,out2,out3,out4); input[7:0] a,b; output reg[6:0] outa1,outa2,outb1,outb2,out1,out2,out3,out4; reg[15:0] outcome; integer i; always @(a or b) begin outcome=0; for(i=1; i<=8; i=i+1) if(b[i-1]) outcome=outcome +(a << (i-1));//移位相加 match(a[7:4],outa1); match(a[3:0],outa2); match(b[7:4],outb1); match(b[3:0],outb2); match(outcome[15:12],out1); match(outcome[11:8],out2); match(outcome[7:4],out3); match(outcome[3:0],out4); end task match; input [3:0] a; output [6:0] b; case(a) 4'H0:b=7'b1000000; 4'H1:b=7'b1111001; 4'H2:b=7'b0100100; 4'H3:b=7'b0110000; 4'H4:b=7'b0011001; 4'H5:b=7'b0010010; 4'H6:b=7'b0000010; 4'H7:b=7'b1111000; 4'H8:b=7'b0000000; 4'H9:b=7'b0011000; 4'HA:b=7'b0001000; 4'Hb:b=7'b0000011; 4'Hc:b=7'b1000110; 4'Hd:b=7'b0100001; 4'He:b=7'b0000110; 4'Hf:b=7'b0001110; default:b=7'b1111111; endcase endtask endmodule