第一步：畫出原理圖

第二步，將畫出的原理圖利用硬體語言實現

module fsm_cola_ctrl( input wire sclk, input wire rst_n, input wire [1:0]pi_money, output reg po_cola, output reg po_money );

reg [4:0] state; parameter IDLE =5’b00001; parameter HALF =5’b00010; parameter ONE =5’b00100; parameter ONE_HALF =5’b01000; parameter TWO =5’b10000;

[email protected](posedge sclk or negedge rst_n) if(!rst_n) state<=IDLE; else case(state) IDLE: if(pi_money == 2’b01) state <= HALF; else if(pi_money == 2’b10) state<=ONE; else state <= IDLE; HALF: if(pi_money == 2’b01) state<=ONE; else if(pi_money == 2’b10) state <= ONE_HALF; else state <= IDLE; ONE: if(pi_money == 2’b01) state <= ONE_HALF; else if(pi_money == 2’b10) state <= TWO; else state<=IDLE; ONE_HALF: if(pi_money == 2’b01) state<=TWO; else if(pi_money == 2’b10) state <= IDLE; //不找零 出可樂

[email protected](posedge sclk or negedge rst_n) if(!rst_n) po_cola<=1’b0; else if(state == ONE_HALF&&pi_money == 2’b10) po_cola<=1’b1; else if(state == TWO && pi_money == 2’b01) po_cola<=1’b1; else if(state==TWO&&pi_money == 2’b10) po_cola<=1’b1; else po_cola<=1’b0; //當時我將找零跟出可樂寫到同一個模組當中，導致編譯通過測試顯示高阻態

[email protected](posedge sclk or negedge rst_n) if(!rst_n) po_money<=1’b0; else if(state == TWO&&pi_money == 2’b10) po_money<=1’b1; else po_money<=1’b0; endmodule

第三步，寫測試模組

`timescale 1ns/1ns module tb_fsm_cola(); reg sclk; reg rst_n; reg [1:0]pi_money; wire po_cola; wire po_money;

initial begin sclk=0; rst_n=0; pi_money=0; #20 rst_n=1; end

always # 10 sclk=~sclk; always # 50 pi_money={$random}%3;

fsm_cola_ctrl fsm_cola_ctrl_inst( .sclk (sclk ), .rst_n (rst_n ), .pi_money (pi_money ),

	.po_cola		(po_cola	),
	. po_money      ( po_money  )

); endmodule

第四步，將模擬影象P出來